Waveform Generator Project

[void_error]

The filter to keep the triangle in shape would be a bessel type filter. But I am not sure its really worth it, because of the limited number of sample in the triangle. At odd frequencies this will cause some kind of jitter, as from the DDS not all periodes will look the same. A filter might also help at the very low frequencies (e.g. < 10 kHz), to avoid the discrete step appearance - though 10 Bits is allready quite high resolution. This filter could than likely be a active filter with OPs.

That's why I didn't bother to simulate a Bessel filter.
Are you suggesting a separate filter only to be switched in for low frequencies?

With the elliptc filter, the first zero should be somewhere near 12,5 MHz - so 10 MHz Limit might be a little high.

It does indeed need some tweaking. I'll do it this weekend.

Have you thought about using an FPGA like the Altera MAX 10 instead of the AD9832?
The cheapest one can be found for 6,46€ on Digikey in quantities of 1.
Configured as a fast 4Kbyte RAM + Address-Counter and using the internal PLL to make the Output-Clock Variable, these FPGAs would add full arbitrary waveform capability to your design. With 2000 Logic-Elements, the cheapest MAX 10 should also be able to generate Sine, Square, Triangle and Sawtooth from mathematical formulas in real-time.
The output of the signal could be a simple Resistor-Ladder, which effectively would give you a DAC that can run at about 400MS/s!
With a half-decent analog part, this system could easily beat these cheap chinese signal-generators you can find on ebay. Maybe not in terms of price, but definitely in terms of quality

The disadvantages though: These devices come in 144pin TQFP-Packages, which basically can only be reflow soldered (A 20€ Pizza-Oven, Multimeter Temperature-Sensor and some solder-paste can take care of that), and their configuration has to be developed and programmed.

Going FPGA is definately not an option, given the fact that I know close to nothing about them and the time it takes to learn to use one. I need the waveform generator working within roughly a month so I could test other projects I'm working on. It's not a big rush but I don't want to waste time either.

[SundayProgrammer]

Going FPGA is definately not an option, given the fact that I know close to nothing about them and the time it takes to learn to use one. I need the waveform generator working within roughly a month so I could test other projects I'm working on. It's not a big rush but I don't want to waste time either.

You are probably aware of this but I I'll link it anyway:
http://alternatezone.com/electronics/dds.htm

It might give you some design ideas (I used this circuit as a starting point for mine).
Low quality image of my latest func gen attached - if anyone interested.

Axel.

[SundayProgrammer]

http://canada.newark.com/analog-devices/ad9106bcpz/dac-quad-12bit-180msps-lfcsp-32/dp/52W9437?MER=ACC_N_L5_SemiconductorsToolsAndAccessories_None

What a beast! 

[Kleinstein]

Using a FPGA todo DDS is an option if you need arbitrary waveform as well. But you likely still need a resonable qualitiy (>=10 Bit) DAC - that may not be much cheaper than the DDS chip. The sine Wave will normally be DDS stype, so with adder for the phase and a resonabel size Sin - table, not just stupid counter and table. With an arbitrary generator, one might even need an auxillary DDS, just to make the variable clock that controls the arbitray generator - here DDS inside an FPGA might be an adequate solution as a 6 Bit R2R ladder might be good enough.

At the low end, there migh be the option to use a small ARM µC, to do DDS in software. Some even have a resonable DAC included. This like a skaled up version of the cheap AVR based sowftware DDS.  Even than you need  a low pass filter for resoanable performance.
 

[Deathwish]

What a beast! 

go to the uk farnell / element 14 site and its way more expensive and they have an eagle footprint for it which the one linked here doesn't. I dont get why there is such a price difference or why they haven't put the eagle footprint on the newegg site.

http://uk.farnell.com/analog-devices/ad9106bcpz/dac-quad-12bit-180msps-32lfcsp/dp/2254929?jsValue=http%3A%2F%2Fwww.farnell.com%2Fcad%2F1713215.zip&jsAction=cad&skipCache=true

[void_error]

Tweaked the filter. Each cap is two identical value caps in parallel. Is it better now?

[void_error]

Tweaked the filter. Each cap is two identical value caps in parallel. Is it better now?

... and stupid me designed the filter for 200 ohms instead of 300 and realized that after clicking the post button so he re-tweaked it and here it is:



First zero is at 12.5MHz in theory, that'll vary with component tolerances.

Ran into another small issue: I'm currently using a trimmer to cancel the DC offset after the filter at the DDS output but I'd like to automate that, so no tweaking is required, the MCU would handle the offset removal at power-on.

I suppose I could use a precision rectifier and set the DDS to output 1kHz, get the offset value (minimum value of the rectified signal) using the on-board ADC then null the offset with a DAC.
Using the circuit shown in Figure 3 of this document, the first op amp being the DAC's output buffer op amp.

Does anyone see any drawbacks in using this?

[void_error]

I suppose I could use a precision rectifier and set the DDS to output 1kHz, get the offset value (minimum value of the rectified signal) using the on-board ADC then null the offset with a DAC.
Using the circuit shown in Figure 3 of this document, the first op amp being the DAC's output buffer op amp.

Does anyone see any drawbacks in using this?

Really stupid and expensive idea. Got a better one.
Set the DDS to 10-100Hz triangle. Get the minimum and maximum amplitude of the triangle using the ADC. Average them to get the offset. Set a DAC output to null the offset then measure offset again and adjust the DAC output accordingly. Schematic coming as soon as it's complete.

[Kleinstein]

Correcting DC does not need a special test signal: there are 3 cases to handle:
1) at high output frequencies (e.g.  > 100 Hz) a simple low pass filter can be used to separate the DC offset from the output. The µC internal ADC could than measure it. The at the lower end the µC might use a digital filter (e.g. averaging over whoule periods) to improve.
2) at rather low frequencies (e.g.  < 10-100 Hz), the low pass filter is likely not sufficient. So the ADC should do the sampling of the rather slow signal and calculate the DC Offset from min/max values or averages.
3) if the Frequency is very low (e.g. < 1 Hz), or as an initial value, the old DC offset is likely the best bet, as there is no measured new DC values available.  So at startup a short test Signal might help, if no old value is saved.

For amplitude control, some kind of rectifier / amplitude measurement might be helpful.

[void_error]

Correcting DC does not need a special test signal: there are 3 cases to handle:
1) at high output frequencies (e.g.  > 100 Hz) a simple low pass filter can be used to separate the DC offset from the output. The µC internal ADC could than measure it. The at the lower end the µC might use a digital filter (e.g. averaging over whoule periods) to improve.
2) at rather low frequencies (e.g.  < 10-100 Hz), the low pass filter is likely not sufficient. So the ADC should do the sampling of the rather slow signal and calculate the DC Offset from min/max values or averages.
3) if the Frequency is very low (e.g. < 1 Hz), or as an initial value, the old DC offset is likely the best bet, as there is no measured new DC values available.  So at startup a short test Signal might help, if no old value is saved.

For amplitude control, some kind of rectifier / amplitude measurement might be helpful.

The DC offset will be removed between the Cauer filter at the DDS output and the AD603. Not sure if those inductors like DC current through them...

I'm assuming the removal of the offset just after the whole thing has powered on will be enough, I don't think it will vary much with frequency. There will be an option in software to recalibrate using the low frequency (10-100Hz) test signal as the offset will probably drift with temperature.

I'm currently planning to use the PIC's on-board reference which is +/-4% over the -40C to +125C temperature range when set to 2.048V with some MCP4911 DACs. Another option would be a more stable 2.5V reference with a resistive divider, 220ohm & 1k gives 2.049V which is close enough but resistor tolerance and temperature coefficient will affect that.

[Kleinstein]

Unless the inductors are extemly small form factor and even lagrer values, a small DC current is not a problem.  It't rather hard to reach saturation at something like 1 mA. DC current is not more than AC peak current. Compensation before the filter is difficult anyway, as the DDS chip would then see negative voltages. Even passive adding at the filter output might be tricky - a little attenuation helps here. However as the AD603 seems to need a rather low input level, it should work.

One will likely need DC adjustment before the VGA (e.g. AD603) to bring the DC level to 0 - here even a manual trimmer might be enough, as DC precission of the AD603 is not very good anyway.

An intentional DC offset at the output would be a different thing, as this should be added after Amplitude adjustment. So it's difficult to use a single DAC to set output Offset and compensate the offset before the VGA. The offest will not change with frequency, but is might change a little with amplitude setting. So the DAC after the AD603 might be used to compensate DC errors from the AD0603 and maybe drift errors from the DDS.

The MCP4911 and similar DACs are not very precise. So there is no real need to adjust the LSB steps to something like exactly 1 mV.

[void_error]

Unless the inductors are extemly small form factor and even lagrer values, a small DC current is not a problem.  It't rather hard to reach saturation at something like 1 mA. DC current is not more than AC peak current. Compensation before the filter is difficult anyway, as the DDS chip would then see negative voltages. Even passive adding at the filter output might be tricky - a little attenuation helps here. However as the AD603 seems to need a rather low input level, it should work.

I'm using the DL0603 and according to the graph it'll do just fine at 1-2mA.

One will likely need DC adjustment before the VGA (e.g. AD603) to bring the DC level to 0 - here even a manual trimmer might be enough, as DC precission of the AD603 is not very good anyway.

That's what the first DAC is for along with a suitable frequency op amp used as a buffer to adapt the filter's output impedance to the AD603's 100ohm input impedance. A second DAC is used to set the gain of the AD0603.

An intentional DC offset at the output would be a different thing, as this should be added after Amplitude adjustment. So it's difficult to use a single DAC to set output Offset and compensate the offset before the VGA. The offest will not change with frequency, but is might change a little with amplitude setting. So the DAC after the AD603 might be used to compensate DC errors from the AD0603 and maybe drift errors from the DDS.

It'll be added after the AD0603. Since modern PICs have a lot of ADC inputs I can do a second calibration to remove the offset of the AD0603 just like I do it after the LC filter and this is where the third DAC comes in, removing the offset at the output of the VGA as well as adding the intentional DC offset.

The MCP4911 and similar DACs are not very precise. So there is no real need to adjust the LSB steps to something like exactly 1 mV.

I know they're not that precise, but they're still better than the 8-bit DAC inside the MCU and they're quite cheap.

A fourth DAC will be used to set the threshold of the comparator which turns the triangle into PWM and sends it out through a different output.

So the first output will be capable of sine and triangle while the second one square and PWM (0-5V amplitude or maybe adjustable in steps like 0-2.5V and 0-3.3V), 10bit PWM being a bit overkill I think... might use the 8-bit DAC inside the PIC.

[Kleinstein]

The input of the AD603 is 100 Ohms, but there is no need to use a high input level. So there is no absolute need for an extra buffer between filter and the AD603. As far as I see it, one might even need an attenuator to reduce the amplitude if one wants to use the full range of the AD603. The DDS Chip can also drive a 100 Ohms filter - just at reduced voltage.
A buffer will of cause help to isolate the DDS chip from the offset adjustment.

For more DAC outputs, there is a dual outut version MCP4921.

[void_error]

The input of the AD603 is 100 Ohms, but there is no need to use a high input level. So there is no absolute need for an extra buffer between filter and the AD603. As far as I see it, one might even need an attenuator to reduce the amplitude if one wants to use the full range of the AD603. The DDS Chip can also drive a 100 Ohms filter - just at reduced voltage.
A buffer will of cause help to isolate the DDS chip from the offset adjustment.

I didn't pay attention to the output buffer gain - it's about 36 minimum which means I need to attenuate the DDS output more, 50 ohm instead of 200 maybe? Pretty easy to do since the DDS output is current not voltage. I'm planning to have a 2V_PP max signal at the AD603 output. Some math needs to be done here.

For more DAC outputs, there is a dual outut version MCP4921.

You mean MCP4912. Using three single output DACs instead of a dual and a single costs a bit more but simplifies the software and PCB layout a bit. One extra MCU pin for chip select isn't that big of a deal. For setting the duty cycle 8 bits should be enough - using the PIC16F1709 internal DAC buffered via one of the PIC's op amps.

[void_error]

Apparently I haven't been able to do much with this project recently due to various reasons so it's gonna take me a while to finish it (I'm hoping this year).
However, I've got this far:

• Changed the DDS chip again, now using an AD9835 because I want to go up to 10MHz.
• Still have to recalculate the DDS output filter for 66 ohms & 12MHz, that is to have a low enough input into the AD603 configured for minimum gain to get 4V_PP output into 1k at 1V gain control voltage.
• Changed the MCP4911 DAC army for a single AD5314 quad 10-bit DAC.
• Using a REF191 as voltage reference for the PIC (2.048V) as well as DDS (divided down to 1.21V using 2k7 & 3k9 resistors).
• The output is driven by a whole AD8052 (both op amps) like it's suggested in this application note, with a 100 ohm resistor at each output.

Am I doing anything completely wrong here?

By the looks of it there's very little chance I'm going to fit everything onto one PCB so I might split it, keeping the fast analog signals on one board. That LeCroy scope teardown gave me a few ideas.

[Kleinstein]

I don't think the AD8052 is such a good choice for the output. I would preferr a SO8 case and possibly higher supply voltage. With the output amplifier, it may not be such a good idea to use a dual OP, as power dissipation may be the limiting factor, at least at higher supply voltages. So cooling the chip can get important.

Also the way of combining the signals is even simpler than in the application note: its two independent identical amplifiers with 100 Ohms each to give 50 Ohms output impedance. The signal for amplitude control and possibly DC control could be from two separate higher value resistors.

[void_error]

I don't think the AD8052 is such a good choice for the output. I would preferr a SO8 case and possibly higher supply voltage. With the output amplifier, it may not be such a good idea to use a dual OP, as power dissipation may be the limiting factor, at least at higher supply voltages. So cooling the chip can get important.

Haven't done the thermal calculations yet but that MSOP-8 package loaded with two op amps will probably not cut it at maximum output voltage & maximum offset. Two single op amps in SO-8 packages will probably be enough but I have to do the math first.

If I want 20V_PP at the output I'll need a +/-15V supply, won't need rail-to-rail (within a few tens of milivolts) output amplifiers but the power dissipated will be higher so that's why I'll stick with 5V_PP and maybe +/-7.5V supply. Output offset will be adjustable between +2.5V and -2.5V when the output is up to 5V_PP and fixed to 0 for anything higher, up to 10V_PP. Regular output stage op amps should be within limits.

EDIT: Found AD826 as a potential output driver. There's also the THS4082 but that's pretty expensive and the THS4062 in a MSOP-8 with an exposed pad which will help with getting the heat away from the die and into the PCB at a slightly higher price than the AD826, all of these are available at TME. I'm trying to avoid Farnell or RS Components because although they stock more types of parts the prices are higher than TME.

I don't see any application where I might need more than 5V_PP with offset.

Also the way of combining the signals is even simpler than in the application note: its two independent identical amplifiers with 100 Ohms each to give 50 Ohms output impedance. The signal for amplitude control and possibly DC control could be from two separate higher value resistors.

How would that DC control look like?

[Kleinstein]

With the amplitude you have to consider that with a terminated cable you loose halve the voltage. So 5 Vpp would be on a high impedance only. So it might allready be difficult to get a valid TTL (or even 5 V CMOS) level on a 50 ohms terminated line with only +-5 V supply.

[void_error]

With the amplitude you have to consider that with a terminated cable you loose halve the voltage. So 5 Vpp would be on a high impedance only. So it might allready be difficult to get a valid TTL (or even 5 V CMOS) level on a 50 ohms terminated line with only +-5 V supply.

How did I manage to overlook that?!
Hmm... this makes everything more complicated. I will have to detect whether the load is high impedance or a terminated cable. Any thoughts on how to do that automatically (using the MCU)?

[void_error]

Any FG I've used is speced into 50oHms so its upto the user to determine the proper amplitude settings under the condtion on which its being used.

If that's the industry standard then I'm sticking with it, no reason to overcomplicate things.

I suppose if its some feature you wanted to add for whatever reason you could use a fast peak detector on the output side of your 50ohm terminating resistor use an adc to read the output of the peak detector that would give you the output voltage at the BNC post.

The only need to limit the amplitude is at the TTL/CMOS output, which is basically the signal coming out of the DDS chip squared using a comparator. If I use a terminator it'll basically halve the voltage at the end so for a 0-5V signal at the terminator I'd need a 0-10V signal at the comparator (which has a 50ohm series resistor between its output and the BNC output connector). If I remove the terminator I will release the magic smoke. Sorry, I'm still almost completely clueless here...

[Kleinstein]

Normally generators give the amplitude at a proper terminated output. Thus half of the open circuit voltage is given. Often there is the option to set / show open circuit volatage instead. If termination is different this is a problem for the user.

If you want to drive a TTL / CMOS input from the FG there are mainly two options:
1) use an unterminated line - so the open circuit signal should be something like 0.5 V / 3 V.
2) use thermination at the input of the circuit board. This usually wil be a soldered resistor of about 47-70 Ohms. In this case loaded output should be the correct level. If termination is lost, this might get a problem to the circuit.

Anyway detecting the real output level will likely not be fast enough to protect a simple logaic gate in all cases. Though logic circuits are often quite forgiving. Otherwise an unterminated line would allready cause trouble. At least extra protection of the output is not commonly found in FGs.

So there is the option to monitor the output after the termination resistor - thus having some kind of SWR meter / impedance bridge at the output. It may be of some use, but I don't know a FGen with that feature.

My main reason to mention termination is because this means the AD8052 will deliver no more than about 4.7 V_pp at the load, including DC offset.

[void_error]

My main reason to mention termination is because this means the AD8052 will deliver no more than about 4.7 V_pp at the load, including DC offset.

You probably missed this. I switched from the AD8052. It won't be used as an output driver anymore.

EDIT: Found AD826 as a potential output driver. There's also the THS4082 but that's pretty expensive and the THS4062 in a MSOP-8 with an exposed pad which will help with getting the heat away from the die and into the PCB at a slightly higher price than the AD826, all of these are available at TME. I'm trying to avoid Farnell or RS Components because although they stock more types of parts the prices are higher than TME.

The THS4062 is tempting and there's also the LM6172.
Not sure which of the above to use...

[void_error]

Had half a day to work on the sine/triangle output stage. Some tweaking may be required and I might have done some things wrong so please point them out.

Here's a simulation with some LT op amps similar (as close as I could find in LTspice IV) to what I found as candidates for the output stage. No bandwidth vs gain calculations have been done yet so I'm using a 5MHz input signal (at least 10x smaller than the bandwidth of the LT1363).

[Kleinstein]

At high frequencies, it is not a good idea to have feedback over 2 OPs. I don't think there is need for an extra amplification stage.

The way to get a 50 Ohms output signal from more OPs in parallel, is to combine the signal from equal amplifiers with resistors of 100 Ohm (for to amplifiers) or 150 Ohms (for 3 units). There is no feedback from the direct output, so the 100 / 150 Ohms resistors are part of the output impedance. Its also a good idea to have some amplification (e.g 2 times) at the output stage, as this usually gives a better stability.
Usually 2 or 3 OPs should be enough for a 50 Ohms output signal.

[void_error]

At high frequencies, it is not a good idea to have feedback over 2 OPs. I don't think there is need for an extra amplification stage.

Thanks, I didn't know that, although I suspected there would be some issues with it...

The way to get a 50 Ohms output signal from more OPs in parallel, is to combine the signal from equal amplifiers with resistors of 100 Ohm (for to amplifiers) or 150 Ohms (for 3 units). There is no feedback from the direct output, so the 100 / 150 Ohms resistors are part of the output impedance. Its also a good idea to have some amplification (e.g 2 times) at the output stage, as this usually gives a better stability.
Usually 2 or 3 OPs should be enough for a 50 Ohms output signal.

That's what I thought about first, then decided to post this instead to get some feedback to whether it's a good idea or not. The number of output op amps will depend on how much power they can dissipate with maximum output swing into a short circuit with the 50ohm times number of op amps resistors in place of course.

U1 will still need to be there for the offset to work, while U3 - U7 will have a gain of about 2.5 and the rest needs to be tweaked.

And another question: Is it better to use the op amps in an inverting or non-inverting configuration?

Oh, and thanks again Kleinstein