Hello, I am searching for ways to convert frequency sweep signal to TTL signal, preferably with ±0.05us accuracy (or maybe worse, then rethink feasibility of the design).
Input signal changes linearly over time from 1MHz to 200MHz, this process is repeated each 50±3us. Period drifts slowly over time.
I am trying to synchronize with this signal without disassembling enclosure of signal source.
Currently I am thinking of these ways:
1) Using band pass / low pass filter with comparator. I thought to use 8MHz crystal (ltspice attached), but it seems that bandwidth is too narrow. I want to avoid any ladder filters which require matching/tuning parts and non-COTS (commercial off-the-shelf) components. RC filter seems doable (in simulation), but I have not tried it in hardware yet.
2) Using 5MHz ADC with 2MHz low pass filter. Idea is to digitize voltage spike: adcPointsPerSweep=(filterBw)/(signalSlope*adcSampleTime)=2.5 [samples]. Maybe need faster ADC, higher cost. time adcSampleTime will give ±0.2 us time offset.
3) Using PLL chip to lock to this signal, then use voltage output.
4) Using FPGA, different approaches
5) Delaying and self-mixing signal
Would be grateful for any help!
Ltspice file uses 16MHz per 4us for save some time (frequency slope is the same as for 200mhz/50us).