Author Topic: What happens after saturation current is reached in inductor and how to simulate  (Read 1153 times)

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Offline DmeadsTopic starter

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Hi all! Messing around with some boost converters.

The Physical inductor I am looking at has a saturation current of 72A, but in my LTspice simulation, the current spikes to almost 160A before reaching SS.

Wondering what will happen in a physical circuit if the saturation current is greatly exceeded?

how can i simulate this?

thanks!

 

Offline T3sl4co1l

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More current, yeah.  Are your aluminum caps modeled with correct ESR?

Saturation can be simulated with a nonlinear inductor.  There's a built-in or library item in LTspice, which I don't know how to use offhand but look it up, it's all documented.  Personally, I use a core model from Meares and Hymowitz:

Code: [Select]
* Saturable Core Model, copied from:
* _SPICE Models For Power Electronics_, Meares and Hymowitz.
*
.SUBCKT INDSAT 1 2 PARAMS: VSEC=1e-4 LMAG=1e-5 LSAT=1e-7 FEDDY=1e6
F1 1 2 VM1 1
G2 2 3 1 2 1
E1 4 2 3 2 1
VM1 4 5 0
RX 3 2 1E12
CB 3 2 {VSEC/500} IC=0
RB 5 2 {LMAG*500/VSEC}
RS 5 6 {LSAT*500/VSEC}
VP 7 2 250
VN 2 8 250
D1 6 7 DCLAMP
D2 8 6 DCLAMP
.MODEL DCLAMP D(CJO={3*VSEC/(6.28*FEDDY*500*LMAG)} VJ=25)
.ENDS

Treat it as an inductor, and couple other inductors to it (e.g. with ideal transformers plus explicit leakage inductances).  LMAG is the low-bias inductance, LSAT is the saturated inductance (so LMAG/LSAT ~= mu_r), FEDDY is the eddy current cutoff frequency (yes, this models losses too(!); set this to approximately the rolloff frequency for the core material of interest), and VSEC is the flux at saturation, approximately equivalent to N*Ae*Bsat for a real core.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 
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Offline DmeadsTopic starter

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yea caps have correct ESR. Thanks. I will check this out. I might try a two stage boost and see what that can do also
 


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