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What is this DOT OR gate in this 8b/10b article?

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Dmeads:
Hey! working on 8b/10b in Verilog. Im using the original 1983 IBM article to structurally code it. Cant seem to find what this gate is (see pic)

All is says is " OR DOT"

any ideas?

Here is the original article. The gate shows up on pg. 11
https://opencores.org/websvn/filedetails?repname=1000base-x&path=%2F1000base-x%2Ftrunk%2Fdoc%2F01-581v1.pdf

ataradov:
I've heard a name "Dot OR" for wired-AND circuit where AND is implemented by connecting two open-collector outputs together. I'm not sure if that makes sense in this context.

Here is a description https://en.wikipedia.org/wiki/Wired_logic_connection

Dmeads:
Okay I did some digging and I found the authors used Motorola's MECL (Monolithic Emitter Coupled Logic) 10000 series chips to implement the design so ya, you're probably right. Thanks!

jmelson:

--- Quote from: ataradov on June 12, 2020, 10:41:38 pm ---I've heard a name "Dot OR" for wired-AND circuit where AND is implemented by connecting two open-collector outputs together. I'm not sure if that makes sense in this context.

Here is a description https://en.wikipedia.org/wiki/Wired_logic_connection

--- End quote ---
In ECL, it is actually a "wired OR" as the gate outputs pull up when active, and let the pull-down resistor control the logic level when not active.  So, if either gate output is active, the logic level gets pulled up to a '1'.

Jon

fourfathom:
Logically it's a NOR gate.

out = !(A | B)

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