Interesting Differential Input/Output Transistor Circuit

[mawyatt]

Can't recall if we have, or if this circuit has been shown before, our memory is fading fast

Attached is a schematic of a somewhat unique differential Input and Output Circuit that can be used for a Frequency Doubler, Square-Law Detector or Full-Wave Differential Rectifier.

Operation Biases each transistor with equal collector currents by means of the "Virtual Ground" as shown in the center of the Differential arrangement which creates an equal Vbe for each device. The Single Ended Input Impedance is equal to the base resistors R7 or R8 (100Ω). Q2 and Q4 Collectors are tied together as are Q1 and Q3 which form the + and - Outputs thru resistors R4 and R2 respectively.

This circuit follows a Square-Law Transfer Function for small signal inputs, and also behaves as a broadband frequency doubler as shown.

In the distant past this circuit was utilized in various custom IC designs as a signal detector, AGC detector, and broadband high frequency doubler operating into MW/MMW region with fast SiGe bipolar devices.

Anyway, we decided to throw one of these circuits together just for fun (see DSO plot), hope some folks find this interesting as well.

Edit: Added LTspice simulation which reflects DSO plot with V1 at 7 volts to produce a collector bias of ~1ma.

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[magic]

Interesting. Looks like it basically produces the absolute value of a differential signal, with some smoothing near zero.

I wonder if similar circuits may be used for slew boosting in opamps.

[mawyatt]

Here's the Transfer Function wrt Differential Current Output vs Differential Input Voltage, which exhibits good Square-Law approximation around the origin. One can solve this analytically (we did long ago) and recall it exhibits good Square-Law fidelity with inputs < |~2Vt|.

The "Differential Center Floating Virtual Ground" keeps the center transistor pair base voltage constant while the outer differential transistors base voltage varies with differential input signal. This causes the center transistor pair for larger input signals to become "input signal modulated" at their emitters by "current hogging" from the differential input devices from the lower current supply source. The subtle effect of the introduction of this Floating Virtual Ground and collector pairing creates an interesting adaptation of the classic differential amplifier, but can't remember where this originated (we didn't invent it), but proved quite useful in many of our custom IC design in the past.

Not sure how one could use this for "opamp slew boosting"?

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[magic]

The idea is that if the differential input voltage becomes large in either direction, all tail current flows through one input transistor into the compensation cap and the opamp slews. You can make it slew faster by detecting this condition and temporarily increasing tail current until the input pair returns to linear operation.

This is said to be common practice in modern opamps, but I have never seen anyone publish a complete circuit. One thing which such circuit certainly needs is a "trigger" which responds to differential voltage of either polarity in the same way.

[mawyatt]

We used a version of this circuit to Detect the presence of particular Signal(s) and "Trigger" a signal processing "Event", and this needed to happen very quickly. In the opamp case the trigger level might be a Vbe junction or fraction thereof.

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[KE5FX]

So all three pins of Q2 and Q4 are tied together?   No need for any current-balancing measures?  Would it work with only 3 transistors?

[magic]

It should work similarly, but you wouldn't get exact zero differential output when the inputs are equal, and maybe a slightly different curve.
Though honestly, you still won't get it exactly due to the 100Ω base resistors dropping some voltage.

You also won't get it if the transistors aren't matched perfectly, such as outside of SPICE...

[mawyatt]

So all three pins of Q2 and Q4 are tied together?   No need for any current-balancing measures?  Would it work with only 3 transistors?

You want the "center transistor" to conduct 2X the bias of the input differential transistors, thus the choice of 2 paralleled transistors. A single device would cause a offset current in the output. On an IC transistors are almost identical, especially with a tight layout, for discrete devices you'll see some variation.

WRT the input resistors having a bias drop, it's low @ (Ic/Beta)*R which is just 1mv with Ic of 1ma, Beta of 100 and 100Ω, nothing to worry about for discrete use, as the individual transistors will likely have more of a Vbe difference than 1mv!

In our chip designs these resistors were 50Ω but we didn't have any 50Ω resistors in hand so just used 100Ω instead for the Protoboard use.

Honestly we didn't try to match any of the 2N3904s, just grabbed 4 from the parts tub, a handful of resistors and plugged things into a Protoboard.

Here's what the kludged up Protoboard looks like. The white dots on the transistors are for device identification, White for 2N3904, Red for 2N3906, Blue for 2N7000. We don't see well and this helps locate devices in the parts tub, resistors are another story .

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[mawyatt]

Here's an example of the Square-Law fit comparing the Output Differential Current to an Ideal Square-Law Current Source with K ~ 0.3.

I = K*(Vin)^2

A good fit until |Vin| > 60mv.

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[Njk]

A good fit until |Vin| > 60mv.

This is at room ambient temperature, I presume

[mawyatt]

Yes.

By making the emitter current source ~ proportional to temperature this improves the overall performance wrt to temperature.

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