Author Topic: Dual slope ADC improvement  (Read 2133 times)

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Online Kleinstein

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Re: Dual slope ADC improvement
« Reply #25 on: October 04, 2019, 07:47:48 pm »
One can measure negative voltage with a dual slope ADC, if one has positive and negative references available.  Alternatively one can use an offset to the input (e.g. zero at the integrator).

With a +7.5 V and -2.5 V supply would allow only 7.5 V as maximum at the input.   The integration cap requirement is set by the maximum input, not the reference voltage.  So it would be C=(integrationTime*Vin_max)/(Vsat*R).   Vsat depends on where the integrator starts.  Starting at 0 and thus allowing 7.5 V at the input there are only 2.5 left for Vsat, if there is no special provision for the reset circuit. So the integration cap would need to be even larger or the resistor larger.  20 ms integration time would also be an option.

For a larger Vsat, one could use a divider or diodes to limit the switch voltage.

To test linearity, at this level the method of choice would normally be a more linear DMM or calibrator  /  Kelvin-Varlay divider.
The main part to worry about is the large range INL, not so much the DNL.

I would expect that the auto zero (reading a zero input) should be done quite often, possible alternating between the signal and zero unless an AZ OP is used. JFET OPs tend to have quite some 1/f noise and thus a short time since AZ really helps. Thus is may be worth considering 20 ms integration - longer integration may not lead to lower noise.  Even than the cycle is allready quite long: 20 ms integrate, 60 ms for disintegrate and a few ms for the capacitor discharge.
 

Offline duak

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Re: Dual slope ADC improvement
« Reply #26 on: October 05, 2019, 05:46:50 pm »
Would it be advantageous to use a zero drift opamp ie., chopper stabilized, for the integrator? This should reduce the 1/f noise but would likely cost something somewhere else.  Any thoughts?

BTW, the closest I got to designing a dual slope A/D was to build a 3 1/2 digit DMM using the Siliconix LD110/111 chipset in 1975.  Siliconix did the hard work and I just followed their lead.  If memory serves it was an integrating design, with a commutating auto-zero and implemented in PMOS + bipolar.  The app note was quite good and goes into more detail than the data sheet.  There's a link on this site talking about the chipset: https://www.eevblog.com/forum/testgear/quality-multimeters-using-sigma-delta/20/?wap2
« Last Edit: October 05, 2019, 09:34:40 pm by duak »
 

Online Kleinstein

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Re: Dual slope ADC improvement
« Reply #27 on: October 05, 2019, 07:06:34 pm »
An AZ OP at the integrator - than likely as a 2 OP integrator, as most of the AZ OPs are relatively slow - could help a little, as it would reduce the 1/f noise. However there would still be the noise of the input buffer, though this could easily be a BJT based OP, as it does not need to be very low bias.  The downside of AZ OPs is often noise at higher frequencies -  so an alternative AZ mode (in sync with the ADC operation) could be higher performance. However it depends on the length of the cycle - this tends to be relatively long for a dual slope ADC (some 60 ms minimum if the range is 2xV_ref).

A cheap AZ OP  (e.g. MCP6V26) has a comparable price tag to a precision JFET OP.  However the availability may be a problem in some countries. Otherwise a ready made ADC chip like ICL7135 or MCP3421 or LTC2451 would be easier and cheaper than building a µC controlled dual slope ADC.

A good circuit to look at, building a dual slope ADC, could be the Datron 1061 DMM, that used a dual slope like ADC (though with an additional slow slope). This is about as good as an dual slope ADC could get.  It uses a possible alternative way for auto zero, combined with the integrator reset.

The old LD110/111 and LD120/121 are already more multi-slope like than a classical dual slope ADC.
 

Online imo

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Re: Dual slope ADC improvement
« Reply #28 on: October 06, 2019, 07:15:05 pm »
 

Offline namster

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Re: Dual slope ADC improvement
« Reply #29 on: October 07, 2019, 11:36:26 am »
@Kleinstein
i was wrong , so I corrected the value of Capacitor and resistor by chosing a 680nF and 47k for integration time of 20ms
Quote
Vsat depends on where the integrator starts.  Starting at 0 and thus allowing 7.5 V at the input there are only 2.5 left for Vsat,
µ
the integration slope is given by Vin/RC so for integration time of Tin the output of integrator will Rise from 0 to a given voltage , for a maximal voltage of 7.5V the output will be 7.5V after Tint i don't understend why you said that there only 2.5 left for Vsat .
Auto zero can be done by reading a grounded input , its less complicated than using a AZ opamp no ?
so now i have to do a calibration of the ADC and finalising this one with add a zero Volt input !
@imo
most of links dont work ! but it give some information thank you !
 

Online Kleinstein

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Re: Dual slope ADC improvement
« Reply #30 on: October 07, 2019, 03:25:43 pm »
If the 4053 switch is used for the integrator reset the integrator Output swing would be limited to the supply fo the 4053 and thus some +7.5 V and -2.5 V. With a positive input (7.5 V) the integrator output would swing negative. So the -2.5 V limit would be relevant.

It would probably be better to have a more symmetric supply, like +-5 V and limit the input range to +5 V so one also has 5 V to room to the negative side.  Alternatively one could limit the voltage between the integrator output and switch for the integrator reset, so that the integrator could swing more than -2,5 V.  This usually introduces some resistance and thus would slow down the reset phase a little, but not to bad.

Using a zero input conversion for auto zero is possible. The effect is a little different from an AZ OP: it compensates essentially all offsets, but is slower. So there can be some 1/f noise as the cycle takes quite some time (e.g. 20 ms integrate, 60 ms disintegrate, 5 ms cap reset and the whole 2 times). At the planed resolution it can be still acceptable with a suitable OP.
An integrator offset would also effect the reference.  Relative to a 2.5 V reference an 25 µV error would not be that bad, though possibly visible.
 

Offline namster

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Re: Dual slope ADC improvement
« Reply #31 on: October 08, 2019, 11:54:20 am »
Quote
If the 4053 switch is used for the integrator reset the integrator Output swing would be limited to the supply fo the 4053 and thus some +7.5 V and -2.5 V. With a positive input (7.5 V) the integrator output would swing negative. So the -2.5 V limit would be relevant.
I completely reversed the operation of the ADC , that's it the 7.5 input will be inversed to negative value that will cause saturation problem in switch !
Quote
It would probably be better to have a more symmetric supply, like +-5 V and limit the input range to +5 V so one also has 5 V to room to the negative side.  Alternatively one could limit the voltage between the integrator output and switch for the integrator reset, so that the integrator could swing more than -2,5 V.  This usually introduces some resistance and thus would slow down the reset phase a little, but not to bad.
the major probleme is that i have designed a current source that is supplied by +-15 Volt ! i have to review the all design a correcte that for a single supply for all the instrument , is a linear supply less noisy than a modern Switch mode supply ?

Quote
Using a zero input conversion for auto zero is possible. The effect is a little different from an AZ OP: it compensates essentially all offsets, but is slower. So there can be some 1/f noise as the cycle takes quite some time (e.g. 20 ms integrate, 60 ms disintegrate, 5 ms cap reset and the whole 2 times). At the planed resolution it can be still acceptable with a suitable OP.
An integrator offset would also effect the reference.  Relative to a 2.5 V reference an 25 µV error would not be that bad, though possibly visible.
do you have an example of AZ opamp , is the ICL7650 a good choise ?
 

Online Kleinstein

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Re: Dual slope ADC improvement
« Reply #32 on: October 08, 2019, 03:05:26 pm »
A linear supply can be lower noise than a typical switched mode. However a well designed switched mode supply can be good enough. There are just more point's that can go wrong with a switched mode supply.  For the first test there is likely no need to use a SMPS: the supply current should be relatively low and thus a linear regulation should be acceptable.

The IC7650 is an old AZ OP, and OK.  Some modern low cost ones are MCP6V27 and similar. The AZ OP does not need to work with a high supply. There is no absolute need for an AZ OP. A good quality normal OP and using the zero reading can be good enough. Also an AZ OP does not solve all drift problems: there is still drift from leakage currents and the buffer amplifier.

How does the circuit to the PCB look like ?  Maybe it does not take so much change and the board could still be used. For a little higher supply there is the old and slightly slower CD4053 / HEF4053, that allow a little higher supply (up to 20 V in the B Version).
 

Offline namster

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Re: Dual slope ADC improvement
« Reply #33 on: October 10, 2019, 12:31:36 pm »
Quote
A linear supply can be lower noise than a typical switched mode. However a well designed switched mode supply can be good enough. There are just more point's that can go wrong with a switched mode supply.  For the first test there is likely no need to use a SMPS: the supply current should be relatively low and thus a linear regulation should be acceptable.
i will try to do a linear PSU for the analog part of circuit and a SMPS for digital and auxiliary psu to start the instrument from a button in front panel
Code: [Select]
How does the circuit to the PCB look like ?  Maybe it does not take so much change and the board could still be used. For a little higher supply there is the old and slightly slower CD4053 / HEF4053, that allow a little higher supply (up to 20 V in the B Version).there is several circuit in first version , i will draw a new pcb that containt differents part of instruments ,thank you for all the interest you have on this subject
 

Online Kleinstein

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Re: Dual slope ADC improvement
« Reply #34 on: October 10, 2019, 03:27:40 pm »
For the first test it should be good enough to use a solder-less bread board. No need to design a PCB so early - the final PCB version may give a slightly lower noise and better linearity, but usually not that much. For my multi-slope version I started with a bread board for the analog part and an small reused PCB similar to the Arduino. One can also start with simple parts (e.g. cheaper OPs) and simple resistors.
 
The first step is to get a suitable schematics and at least a rough idea of the software. The software can also limit the timing resolution.
For a Ohms meter one may not need negative values, at least not much range to the negative side. Another question is if oone needs /wants a (quasi) differential measurement.
It can help to draw not just one solution, but also a few alternatives to compare them (expected performance, size/cost and software requirements). The first round can be just from the drawing, maybe with a simulation if needed. Chances are one can decide on paper which solution is suitable.
 
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Offline namster

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Re: Dual slope ADC improvement
« Reply #35 on: October 11, 2019, 10:35:56 am »
i have started this project last years ,it was a projet for my final years graduation i started with design schematic and testing in breadboard , because a lack of time i had to realase the PCB , and now i wan't to continue the devlopement of my instrument to have a final product that work correctly , the negative value is used to measure the voltage across resistance with reversed current that give two inversed voltage to reduce the Thermal EMF ,I am now trying to correct the problems i encountered
 


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