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Whats the craziest you've run a mosfet in avalanche? (or seen run?)

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cur8xgo:
How much power have you seen dissipated in avalanche in a mosfet in a working design, intentionally?

Lots of big TO-247 fets out there are explicitly thermally limited for avalanche so the sky is the limit basically. Wondering whats been done. (and why its been done)

T3sl4co1l:
No idea.  I don't look at a lot of bad designs in enough detail to know that.  I avoid using avalanche in my designs, if at all possible.

Some examples I can think of, mostly use terrifically slow switching to avoid avalanche in the first place.  Replacing bad with worse, but if it works in the average case, they'll go ahead and sell it...

Tim

cur8xgo:
Why is using avalanche bad design? Vishay has made it clear which of their fets are designed for it and those are limited only thermally. Makes an inexpensive and simple way to snub switching transients, since when its a factor you probably already have huge heat sinks on the fets. https://www.vishay.com/docs/90160/an1005.pdf

MagicSmoker:

--- Quote from: cur8xgo on June 04, 2019, 01:33:18 am ---Why is using avalanche bad design?

--- End quote ---

Avalanche is perfectly fine *if* the source impedance and/or the peak current is limited; if not, then device destruction is likely. Generally, avalanching a transistor (of any flavor) is only done when the fastest possible demagnetization is required switching an inductive load (think relays, contactors and the like; not transformers, except for old-style "transistorized" Kettering ignition systems).

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