Is t_CAC delay in SDRAM due to signal propagation delay?

[Axk]

This question is out of curiosity, I'm not solving any problem here, I'm sure one can successfully control SDRAM without this knowledge.

The question is why t_CAC (the time between the CAS pin going low and valid data available on the data pins, where CAS*t_clk >= t_CAC) is not measured as a constant number of clock cycles independent of the clock frequency, but is a fixed time constant independent of the clock frequency)

I understand that the activation phase is asynchronous with the time taken by charge transfer between row capcitors and bitlines and apmplification, but once a row is active it should be just a matter of clocking out the values from the outputs of the amplifiers.

Then does it mean that t_CAC is purely due to the signal propagation delay through all the combinational logic between the outputs of the sense amplifiers and the data pins?