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Which Logic Buffer Should I Use?

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PsychedelicBreakfast:
Hello all,

I'm using CPLDs to drive another CPLDs - essentially, a Serial In Parallel Out shift register (driving end) is connected to a Parallel In Serial Out shift register (receiving end) via some long (~10m) wires.

After some advice from here and other forums, I think it's a idea to protect my outputs via buffers. However, should I use buffers on both ends of the wire i.e. at the output and the input?

Today, I used a ULN2003 darlington array as a buffer. The weird thing was that the output voltage, when low, was 0.7V instead of the expected ~0V. I had a 1K pull up resistor between the collector and Vcc. Is 0.7V for low expected?

The input did read everything okay - the 0.7V voltage was read as low, as expected.

But should I look into using dedicated logic buffers? My requirements are to protect the device from ESD damage, reduce EMI and 3.3V operational voltage. Any suggestions?

EDIT: wanted to add, the wires are expected to be short circuited. That's what I'm trying to detect! So, the buffers should be such that when a wire that's Low is short-circuited with a wire thats High, it should also become High.

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