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Electronics => Projects, Designs, and Technical Stuff => Topic started by: electronx on August 12, 2023, 12:21:00 pm

Title: Why CPU DDR Memory Controller Has 2 Clock Outputs?
Post by: electronx on August 12, 2023, 12:21:00 pm

I'm trying to understand the ddr structure for the iMX6 Rex Module. The CPU used is the MCIMX6Q5EYM10AC model from the nxp i.mx quad series.
https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf (https://www.nxp.com/docs/en/data-sheet/IMX6DQCEC.pdf)
https://www.imx6rex.com/wp-content/uploads/2016/04/iMX6-Rex-Module-Schematic.pdf (https://www.imx6rex.com/wp-content/uploads/2016/04/iMX6-Rex-Module-Schematic.pdf)
A configuration was made using 4 x16 DDR3 DRAM, with a total of 64 word lengths. So far everything is great. Why are there 2 (DRAM_SDCLK_0, DRAM_SDCLK_1 ) clock outputs?Does it matter from which clock source we feed the ddr chips?
(https://i.stack.imgur.com/7la4U.png)
(https://i.stack.imgur.com/4EDt7.png)

Title: Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?
Post by: DavidAlfa on August 12, 2023, 12:50:15 pm

Because it's a differential signal!
(https://www.edn.com/wp-content/uploads/media-1109140-fig2.gif)
https://www.edn.com/double-data-rate-sdramthe-next-generation/ (https://www.edn.com/double-data-rate-sdramthe-next-generation/)

Title: Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?
Post by: ejeffrey on August 12, 2023, 12:54:35 pm

That's not it, the diagram shows two differential pairs.

Title: Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?
Post by: DavidAlfa on August 12, 2023, 01:17:34 pm

Ah didn't see he bottom one!

Quote

DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality extremely important. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated. (Other topologies use a tree structure, where termination is off the module near the connector.)

https://www.micron.com/support/~/media/D546161C2C6140BCB0BAEE954AA53433.pdf (https://www.micron.com/support/~/media/D546161C2C6140BCB0BAEE954AA53433.pdf)

Title: Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?
Post by: electronx on August 12, 2023, 01:34:30 pm

Quote from: DavidAlfa on August 12, 2023, 12:50:15 pm

Because it's a differential signal!
(https://www.edn.com/wp-content/uploads/media-1109140-fig2.gif)
https://www.edn.com/double-data-rate-sdramthe-next-generation/ (https://www.edn.com/double-data-rate-sdramthe-next-generation/)

Thanks for your help. but I'm not as noob as you think  :D
two different clock source (every clock source is differential signalled)

Title: Re: Why CPU DDR Memory Controller Has 2 Clock Outputs?
Post by: DavidAlfa on August 12, 2023, 03:01:41 pm

It's all your fault, you should have stated 4 clock signals!   :D