Probably not very worthwhile, or follows similar patterns to other diodes.
Though the latter seems suspicious, as the characteristics are notably different -- for one, they're slower than optimized diodes are, but the forward recovery is also suspiciously low (which seems strange given the slow t_rr). And in my measurements it doesn't seem attributable to the fact that, if Vgs = 0, the channel conducts when Vds < Vgs(th): this should act to clamp the forward recovery voltage but not shorten or eliminate it, whereas it seems to simply be absent.
So, aside from some background information, I'm afraid I don't have much to help with the stated problem.
I can offer advice on avoiding the stated problem entirely.
The body is never forward-biased when synchronously rectifying (that is to say: there is not even any point in doing it, if Iout * Rds(on) > Vf so that body conduction occurs), so this information is only needed during commutation: when the rectifier turns off, before the opposing switch turns on.
So, simple enough: don't do that.
Set dead time to zero, so that the switches are either exact, or even slightly overlapping (negative deadtime, shoot-through).
Doesn't this fuck everything up? Take a closer look at the system. Where does the current flow? "Short" current flows in the switching loop. If we know the inductance of that loop, then the current flow is not simply "short circuit current", but a ramp at dI/dt = V/L. If dt is small say 20ns, and L is modest say 50nH, and let's say supply is 30V, we'll have dI = 12A. Maybe quite a lot for a small converter, but if we're doing more like 50A output, we won't really miss it, will we?
The energy absorbed by the switching loop, still needs to go somewhere, so we need some manner of clamping or loss to deal with it. 50nH is high enough that a clamp snubber is feasible; simply design it for maximum peak voltage at maximum load current plus commutation current (the dI above). For the above case, say we're using 60V transistors and a maximum 40V input so a nominal-max 20V overshoot is acceptable. The snubber must have less than 8nH loop inductance to the transistor (which is feasible for SMTs; TO-220 would blow this handily, however!), and an RC of < 0.4Ω and C > 0.3uF, or an RCD clamp with C >> 0.3uF. The maximum charge (of the loop inductance) is 50 + 12A so the energy is 96uJ; at 200kHz this is 19W dissipated in the resistor. (For the clamp case, this power can be "stirred" back into the supply using a buck-boost converter; it's not usually worth the bother, though.)
I have no idea if these values are at all representative to what you have in mind, but the relations are there in any case.
If you're using a controller, unfortunately you likely have no way to optimize its timing (dead time). Worse still, its timing variance may be too gross to be able to do a good job with external compensation (which can be done with RCD networks to give asymmetrical delays, and external gate drivers if sharp gate edges are still required). That is to say, maybe you can adjust one unit to an acceptable balance, but how well will that hold in production? How far was your prototype from "typ", and what is the real variance in that spec? (At least, the way it's usually done is, I think, +/- 3σ as a truncated normal distribution, so you're pretty unlikely to get a truly bad one. Still, that's some minimum amount of production failures that must be discarded or reworked, and definitely not great if a single board has more than a few channels, making it more likely that at least one controller has poor timing.)
Tim
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