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Why is my regulator's transient response so bad?
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mck1117:

--- Quote from: schratterulrich on February 15, 2020, 10:09:23 pm ---Then I have included an available LDO regulator - LT1962-3.3 - i really don't know if it has similar characteristics as your LDO. It's just for experimenting

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That's an interesting choice - that regulator looks like it might actually be the same thing as the TLS203/205.  The datasheets are just too similar to not be the same chip...



That's some great analysis though.  I think I'll try first swapping out a few of the 100n caps with 4.7uF (better voltage derate, plus "just add more capacitance"), then bodgewiring in a 100uF tantalum or something ("just add more capacitance, part 2"), and see what happens.
T3sl4co1l:
Curious, if it's designed as a 2nd source equivalent (which sales might request internally, or a customer might request to get supplier coverage) it's strange they didn't go all the way and use equivalent packages as well.

Tim
David Hess:

--- Quote from: mck1117 on February 15, 2020, 03:16:34 am ---Slightly different 3.3v rail capacitors.  I have all ceramics, and ST used mostly ceramics but a few tantalums, but only for VDDA and VREF+ (but not the cap right next to the regulator - that one's ceramic)

...

Besides, 120khz is much too slow for an LC resonance somewhere on the board.
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These two things are consistent with compromised frequency compensation because of an output capacitor with too low of an ESR.


--- Quote from: mck1117 on February 15, 2020, 03:54:31 am ---The datasheet claims that it's stable with ceramic caps, but maybe they define what I'm seeing as stable (which it technically is, I suppose).

Looking at this TI doc: http://www.ti.com/lit/an/slva115a/slva115a.pdf, it claims that fewer than 4-ish rings on a load step indicates sufficient phase margin for stability, and I'm seeing...almost exactly 4, so it's pretty borderline.
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Whether that level of stability is acceptable depends on the application but there is an issue with reliability over time and temperature if the stability is marginal.

There might be something else you can do other than adding ESR in series with the output capacitor in the traditional way.  Figure 7 in the Infineon datasheet shows the connection for remote load sensing.  Add the ESR as Rp as shown in series with the output and connect SENSE as shown to the output capacitor.  This connection is commonly used with regulators which implicitly support zero ESR output capacitors whether shown or not.  Whether this works or not depends on exactly what the BYPASS connection is doing but figure 8 gives me hope that it is working as a high frequency AC feedback path.
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