Looking at the nice 1µs sampling pulses, and how the hold capacitor gets charged to 95% of the peak value at the first sample, I'm wondering, why can't I make this same pulse width work for lower frequencies?
In the original design, the timing capacitor is 1nF, and this worked well for 100Hz-10kHz. Above 20kHz, it failed to produce a sampling pulse, because the capacitor, when the first comparator output went high, pushed the input of the second comparator to well beyond 20V, and it failed to discharge below 0V again in time to trigger a pulse. My diode trick with D3 solved this. 1nF produces a pulse of approx 10µS, which is obviously too wide for 100kHz operation, so 100pF was needed for the upper frequency decade. But the hold capacitor did not reack the full voltage from the peak hold capacitor during the sampling window of 1µs, so several pulses were required for the output to settle. No problem at high frequencies, but this would also mean that the settling time increases with lower frequencies. Hence the rationale for timing capacitor value anti-proportional to the frequency decade.
Once I realized that the charging of both capacitors was current-limited by the opamps, and found a faster, higher-current opamp (LM6171/6172), the hold capacitor consistently charges from zero to 99% of the peak value during one sampling pulse, regardless of input frequency. Now, what's the use of wider sampling pulses at lower frequencies? 100pF timing capacitor / 1µs pulse worked fine down to a couple hundred hertz, then problems arose. After some investigation I found the cause: For the lower frequencies, the input signal rises relatively slow, and as it passes zero - and the voltage at the peak hold capacitor C1 - the comparator U4 is tricked (probably noise contributes to this); the output goes high, then the positive input momentarily appears lower than the negative one, so the output goes low, triggering a sampling pulse, before it goes high again, allowing C1 to charge. In effect, it triggers sampling when the input is a zero. In the original circuit, there was hysteresis added to this comparator, in the form of positive feedback. Removing this was the first modification I made, as I thought it would delay sampling slightly, thereby increasing the voltage drop of the output with respect to the input, due to the LED in antiparallel with D1 that let C1 follow - but lag - the input signal during the entire cycle. Now, with that diode/LED arrangement gone, The hysteresis can safely be added again. Values of R6 and R7 adjusted to accommodate for the smaller pull-up resistor at the collector output of U4.
Now the sample&hold peak detector works 100% flawlessly, across the entire intended frequency range, the output immediately reflecting the input peak, with a fixed sampling pulse width of 1µs. Done, now it's oscillator time
/Richard