Wien Bridge project

[richlooker]

Thanks for the suggestion, Tim 

I wonder if it would be worthwhile, to add another op-amp to assist the schottky?  It's clearly the weak link, as a tempco offset.
I think the approach would be... wire U1a as a precision rectifier, but not actually because its buffered (well, amplified too) signal is needed elsewhere -- so it would add another op-amp.  Also, it needs to be rather fast slewing (even with the diode-from-output-to-input clamping trick).

- I have pondered over this. And simulated it. It resulted in a hell of a lot of osillation, since the peak tracking voltage - as the input signal rises from zero towards peak - is almost the exact same voltage as the input signal, and the comparator that is supposed to detect that the input signal has passed the peak and is falling, now goes crazy. It can probably be solved, but I think the circuit is already somewhat overkill for the purpose, so I'll leave it at that.

It would be nice to not discharge C1 all the way as well, both giving U1a (or the precision recitifier) an easier time and reducing required voltage changes; I'm not sure exactly how to do that here.  It would be nice if the peak can be sensed by comparator, without having to differentiate it (which would likely add yet another wafer to the switch).

I mean, you're already differentiating it, that's effectively what U3 is doing -- which means that might be a good section to investigate further.  Specifically, D1 leakage is the limiting factor, and C1 reactance rises at low frequencies so noise goes up as well, which introduces phase noise which I guess puts a bit of variance on the output (earlier/later sampling results in an incrementally lower voltage, either during the rising edge before C1's voltage has reached peak, or the falling edge as C1 discharges into leakages?).

I suppose that's another nice thing about quadrature, you have zero and peak crossings available implicitly.  Wonder if any node, or branch [current], in the Wien bridge does?  I'd have to think about it..

I may experiment with these suggestions at a later time, but right now the precision I could gain is not needed. But whenever I need a precision peak detector, I know where to start tweaking

/Richard

[richlooker]

Device under test.




It draws something like 20mA from both positive and negative supplies (I <= 15mA < 25mA).



First test, with a 10kHz signal. 3Vpp signal (amplified from 1Vpp by U1a) and output:




6Vpp signal and output. What you don't see here is that the output changes instantly and with no wobble whatsoever.




Sampling pulse with C2=1nF: (wish I had more than two scope channels, so I could see more things at once)




And with C2=100pF:

[richlooker]

10kHz - 100kHz doesn't work very well, and it won't until I get the faster opamps. The lower end of the frequency range did not work at all with the original design. Here is what it looks like now.

10Hz signal, 6Vpp, C2=100nF, this is what the peak tracking wavwform looks like:




The sampling pulse:




Input signal and sampling pulse:




Output at 6Vpp:




And at 3Vpp:




Again, output level change is instant - stable at first peak - and frequency change does not affect output level.

[Vovk_Z]

Again, output level is instant - stable at first peak - and frequency change does not affect output level.

- it's cool for Wein Bridge type oscillaltor. 

[richlooker]

The goal was to to design a peak detector where;

• Output level is constant/stable over the frequency range 10Hz - 100kHz (this is required in order to have constant amplitude from the oscillator over the frequency range)
• Output level is unaffected by frequency change - no peaks, troughs or wobbling
• Output level changes linearly with input level, over 1V-6V peak-to-peak
• Input level changes are instantly reflected and immediatly stable on output[/i]
  

So far it looks like all these goals are achieved, even though the frequency range 10kHz-100kHz is not yet tested.

I'll put this - the source for feedback signal to the AGC circuit - to rest for now and concentrate on the oscillator circuit itself.

As I wrote in the first post, I was considering either an amplifier design based on discrete BJTs or using high-speed opamps. I bought a couple of LT1253 - a "low cost dual current feedback amplifier for video applications" with 90MHz GBW and 250V/µs output slew rate, according to the datasheet - but this turned out to not be a good choice; the LT1253 is not unity-gain stable and the noise and harmonic distortion figures are not exactly great. LM6171/6172 should be much better suited, so I'll try a couple of different configurations with those once I get my hands on them. Until then, I will give the discrete circuit another go; I think it should be possible to configure a JFET-based AGC operating at a low enough Rds range to be usable as a substitute for a filament lamp based stabilization circuit.

/Richard

[richlooker]

As this is a practical project, with an assembled and working sine generator as the final, desired result, my posts will be a mix of theory, simulations, practical testing and physical build considerations - one of these being how to switch all the things that need to be switched. The need for poles/decks in the frequency range/decade switch has exceeded what I have available, I have ordered two (I always buy twice what I need for a project, thereby building a component stock :-)) of these 4-pos/3-deck/6-pole switches:




Five of the poles are already occopied:

• Two for switching the timing capacitors
• Two for switching "phase compensating" resistors per decade - these will ensure that the upper frequency of each decade is exactly 100Hz/1kHz/10kHz/100kHz, then a common 26-step resistor ladder operated by a 2-pole/26-pos switch (photo below) will select the lower frequencies in steps with good enough accuracy
• One for switching the sampling pulse timing capacitor of the peak detector circuit

I'll probably figure out an application for the remaining pole along the way.




/Richard

[richlooker]

As I wrote initially, I was hoping to learn something from this. And I have learned a lot. About JFET characteristics and how JFETS behave in real life. I have learned to use a simulation tool - I chose Tina-TI over LTSpice, because I use lots of TI opamps - out of necessity, so I can test different devices without having to buy them first. I bought a handful of LT1253 opamps, as I believed this was an affordable way to get the bandwidth I need. Then I realized that there is more to an opamp than FET or BJT input, GBW and slew rate. I learned that there is such a thing as a current feedback opamp, and that LT1253 is such an opamp. By properly dimensioning the nfb resistor network I managed to make a somewhat stable oscillator from it, but at a gain of just 3 it's bordering on instability, and it really, really wants to self-oscillate at around 12MHz.

Today I received what I thought would solve all my problems - a handful of LM6171 and LM6172 opamps. Unity gain stable, 100MHz unity-gain bandwidth, 3000V/μs slew rate and 50mA of output current, sounds really good, and looked very good in the simulations. I am sure these will be golden in the oscillator, but in the S&H peak detector I ran into problems. Using 1/2 LM6172 to buffer the input voltage peak hold capacitor worked great, except not at low frequencies. Turns out it has an input bias current of 1.2µA (typical) up to 4µA (max), and at below 100Hz this current charges the 10nF faster than the input voltage rises, both confusing the peak detection and producing a ramp that hits the max output voltage at 6Hz. At 10Hz, with a 4VPP input, this is what it looks like. The red curve is supposed to be a schottky drop below the input voltage, and to stay flat from the input peaks until it crosses zero. There must be something wrong with my LM6172 SPICE model, as this worked 100% as it should during simulation.




The comparator thinks the input signal has passed the peak but in reality it's the capacitor voltage ramp that has risen above the input:




As the S&H tries to sample a rising voltage instead of a constant one, an anomaly is generated on the output voltage (which is supposed to represent the peak of the input)




Solution? I have to insert another JFET input opamp between the peak hold capacitor and the LM6172 input - this should be just fine, as the latter was chosen for it's ability to dump current to the S&H capacitor. New diagram and simulation coming up.

/Richard

[T3sl4co1l]

Could also add a JFET source follower, if you don't mind the potential drift and offset (10s mV?) -- typical strategy is to use a matching JFET as current-regulating diode, thus holding the follower at Vgs=0 and tracking alright with temperature.

Alternately, use a unity-gain buffer instead of another opamp; there aren't as many of these to choose from though, I think?  So probably a bit on the expensive side.  Dunno, I forget which ones are common.

Tim

[richlooker]

Could also add a JFET source follower, if you don't mind the potential drift and offset (10s mV?) -- typical strategy is to use a matching JFET as current-regulating diode, thus holding the follower at Vgs=0 and tracking alright with temperature.

Can you show me schematics for this circuit element?

Alternately, use a unity-gain buffer instead of another opamp; there aren't as many of these to choose from though, I think?  So probably a bit on the expensive side.  Dunno, I forget which ones are common.

Thanks for the suggestions. I can only find one such device - AD8244 quad unity-gain buffer - which costs a fortune. But I have a simpler solution; as I am using a single opamp (TL081), I'll swap that out for a dual (TL072).

Here is the modified peak detector circuit. Added U2a to buffer the C1 voltage; JFET input means bias current in the picoamps range, so should not cause any trouble. I also modified the differentiator circuit; decreased R3 from 10K to 2K, shortening the rise time of U4 output to make it close to a pulse wave, and added D3 to short R4 when U4 output goes high; without this, the negative input of U4 will rise to over 20V as C2 is reversed, and will take several µS to settle at Vcc+.



Simulation at 100kHz, now the sampling/gating pulse is much better defined than before the R3/D3 modifications, making me think this may actually work for 200kHz and beyond. Maybe I should reframe the project to 20Hz-200kHz instead



/Richard

[T3sl4co1l]

Like this:
https://www.planetanalog.com/wp-content/uploads/media-1304480-Image1.png

Oh, there's also a configuration with two opamps cascaded, which increases phase flatness, and might be relevant here (not that phase flatness specifically would be useful, but some combination of that and frequency response would), something to try; or if nothing else you can put U1b in U2a's loop to cancel its offset.  Any time you're putting amps in loops, you need to mind compensation, of course!

Tim

[richlooker]

Looking at the nice 1µs sampling pulses, and how the hold capacitor gets charged to 95% of the peak value at the first sample, I'm wondering, why can't I make this same pulse width work for lower frequencies?

In the original design, the timing capacitor is 1nF, and this worked well for 100Hz-10kHz. Above 20kHz, it failed to produce a sampling pulse, because the capacitor, when the first comparator output went high, pushed the input of the second comparator to well beyond 20V, and it failed to discharge below 0V again in time to trigger a pulse. My diode trick with D3 solved this. 1nF produces a pulse of approx 10µS, which is obviously too wide for 100kHz operation, so 100pF was needed for the upper frequency decade. But the hold capacitor did not reack the full voltage from the peak hold capacitor during the sampling window of 1µs, so several pulses were required for the output to settle. No problem at high frequencies, but this would also mean that the settling time increases with lower frequencies. Hence the rationale for timing capacitor value anti-proportional to the frequency decade.

Once I realized that the charging of both capacitors was current-limited by the opamps, and found a faster, higher-current opamp (LM6171/6172), the hold capacitor consistently charges from zero to 99% of the peak value during one sampling pulse, regardless of input frequency. Now, what's the use of wider sampling pulses at lower frequencies? 100pF timing capacitor / 1µs pulse worked fine down to a couple hundred hertz, then problems arose. After some investigation I found the cause: For the lower frequencies, the input signal rises relatively slow, and as it passes zero - and the voltage at the peak hold capacitor C1 - the comparator U4 is tricked (probably noise contributes to this); the output goes high, then the positive input momentarily appears lower than the negative one, so the output goes low, triggering a sampling pulse, before it goes high again, allowing C1 to charge. In effect, it triggers sampling when the input is a zero. In the original circuit, there was hysteresis added to this comparator, in the form of positive feedback. Removing this was the first modification I made, as I thought it would delay sampling slightly, thereby increasing the voltage drop of the output with respect to the input, due to the LED in antiparallel with D1 that let C1 follow - but lag - the input signal during the entire cycle. Now, with that diode/LED arrangement gone, The hysteresis can safely be added again. Values of R6 and R7 adjusted to accommodate for the smaller pull-up resistor at the collector output of U4.

Now the sample&hold peak detector works 100% flawlessly, across the entire intended frequency range, the output immediately reflecting the input peak, with a fixed sampling pulse width of 1µs. Done, now it's oscillator time



/Richard

[richlooker]

I have spent several hours fiddling around with two different oscillator configurations; variations of single opamp with FET AGC plus dual inverting opamp with optocoupler AGC. The latter is actually less challenging to get oscillating across 10Hz-100kHz, but the gain seems very frequency-dependent, and I have been unable to achieve anything resembling constant amplitude over the frequency range. The FET stabilized circuit seems a lot less frequency-dependent with respect to amplitude, but I have yet to find a resistor combination that will let it start oscillation across the entire frequency range. I also discovered that the instant response of the sample&hold peak detector may lead to problems; I sometimes had the oscillator enter a state where a peak resulted in increased feedback, which made the next peak attenuated, and the immediate feedback made the next peak higher etc. - in other words, the amplitude alternated between two values for every other period. Seems I may have to include an extra time constant in the feedback.

I decided to stop wating hours trying and failing, and try a systematic approach instead. I realized that none of the articles I have found on the internet mention much about variance in JFET characteristics and how to compensate for these. Each and every one of the proposed circuits may oscillate - and without saturation - for one instance of a specific JFET, and not for another one. Rds(on), transconductance and Vgs(off) in general are specified only as typical and maximum values, with very high variance. A practical circuit that depends on these parameters must be tuned for a specific JFET.

While I was measuring the characteristics of a BF245C, my oscilloscope died on me. No big deal, it's an old Picoscope 2204 USB scope, and I immediately ordered a new one (2204A), but while waiting for this to arrive I have to work with simulations.

Tina-TI refused to simulate the sample&hold peak detector with the oscillator, so I put in a simple rectifier circuit for the purpose of simulation. The time constant of this will influence the values, but probably not the gain or the oscillation conditions.

Before my oscilloscope gave up the ghost, I managed to measure the gain of the oscillator amp stage - with the positive feedback elements removed - every decade from 10Hz to 100kHz, and it stayed within 1% except for at 100kHz where it rose with 3%. Still I suspect that with the positive feedback/timing elements the gain will fall off significantly at the higher frequencies. I have been thinking of using an error amplifier with input from a reference peak voltage and the actual oscillator output, but I'm not sure how to do this.

P1 and P2 will allow adjustment for Vgs where Rds starts to rise and Vgs(off), to achieve a certain amplitude (P1 lower setting = higher feedback gain = lower amplitude) but significant Rds(on) variance may require scaling of the negative feedback network of the opamp.



/Richard

[Sengcid]

Hi guys.
For fast amplitude control I use a pair of zeners in the feedback loop (see attached). They clip fairly gently so that the distortion is quite low (OK for a test signal). For very low distortion add a variable resistance in parallel and adjust for borderline oscillation (when you need it). For ultralow distortion use two-stage high gain blocks. For 100kHz you will need some very fast op-amps and careful layout (proto-board not ideal). It seems that the only way around the relationship between frequency and settling time is direct digital synthesis (expensive). Herewith two circuit ideas you could try. For more detail on the theory see my collection of monographs (part 4 monographs 1 and 3).
Chris
Sorry chaps. I have had to remove the link to the cloud. If interested pls pm me.

[richlooker]

Got my new Picoscope, so here we go

I guess I have hit the downside of ultrafast peak detection. The blue trace is tthe oscillator output, red is output from the peak detector:



This behaviour is consistent, regardless of frequency. Only by adjusting down to peak below 1V can I get a stable signal. Tried all kinds of filtering/integration of the peak detector output, but it remains unstable when peak approaches 1V.

[T3sl4co1l]

Hah, is that a stable limit cycle with period 7?  No, it's not quite back where it started, must be more than that...

Welcome to the wonderful world of chaotic sequences.

Presumably, it will help to reduce loop gain, and add a compensation term, so that the amount the amplitude is changed by, is relatively small from sample to sample, but has an overall integral term to give low asymptotic error.

One thing you didn't measure, is response time versus amplitude, or also gain, I think?  If these vary with amplitude, that's a perfect place for nonlinearity to arise, and hence chaos.  In addition to the oscillator's transfer function, which probably isn't very orderly either (if its natural damping coefficient is very small, then the control varies between negative and positive integration).

Tim

[richlooker]

I found the trick was to reduce the gain range the VGC circuit controls, by making R5 as small as possible while also ensuring that oscillation occurs across the entire frequency range when the JFET is fully on (Rds = Rds(on)), and likewise that no oscillation occurs when it is off (Rds = Rds(off)). With the chosen values, gain will be between 2.95 (assuming Rds(on) = 100 ohms) and 3.1. I also found out that the adjustment of feedback gain was not very useful, and fixed gain around 4 gave the best results. Gain is tunde by varying the negative feedback offset with P1. I also found that C4 had to be larger to allow oscillation at the lower frequencies. Currently it shuts down around 30-40Hz, as the impedance of the capacitor becomes high enough to reduce gain below oscillation condition. I have ordered some 6800µF bipolar electrolytics, thinking maybe 13600µF will enable oscillation down to 10Hz, where the impedance will be 0.8 ohms.



This worked nicely at all frequencies down to 50Hz; here is a trace at 100kHz (almost) where the red trace is the feedback DC offset.



There is some noise present, and tendencies to spurious oscillations at 6-25MHz, but not bad for a breadboard circuit. Here with spectrum plot.



And 100Hz with spectrum.

[richlooker]

As long as I kept the timing components on the same breadboard and close to the oscillator opamp, everything behaved very nicely. When I switched to the arrangement here, to be able to switch frequencies by just moving jumper wires, things got more problematic - more noise and more prone to spurious oscillations, but still workable.



When I added this rotary switch for fast frequency switching, the stray capacitances and inductances became too much, and I got severe spurious oscillations, affecting the operating points of the active components such that I could not get the desired oscillation at any frequency. A reflection; I have earlier stated that breadboarding should be unproblematic as long as you work with relatively low frequencies, eg. f <= 100kHz, but I did not consider that the circuits themselves would be induced to oscillate at much higher frequencies



It's now clear to me that the rotary switch and the timing capacitors have to be on the oscillator PCB. I guess I'll have to get the circuit onto a PCB before I can decide on the final component values. Next step: PCB design

[T3sl4co1l]

Why C4 at all? It's ground referenced on both sides, and the JFET shouldn't be rectifying at signal levels (and if it is, reconsider how and where you're using it!).

Which is one of the difficulties of using JFETs as variable resistors, they don't have a wide variable range.  The useful range of Vds is the difference between Vgs and pinch-off; so as Vgs approaches pinch-off, it looks more and more like a symmetrical constant current source with a small resistive step near zero.  Or something like that.  So, high Vgs (near zero) is preferable, and Rds is best varied over a modest range like 1:3 or something like that.

You'll have the same fundamental problem with the fixed time constants in the feedback path -- since your precision detector is discrete-time, so also should be the feedback network.  Use switched-capacitor filters!

Tim

[richlooker]

Hi Tim, thanks for the negative feedback 

Why C4 at all? It's ground referenced on both sides, and the JFET shouldn't be rectifying at signal levels (and if it is, reconsider how and where you're using it!).

I have used the configuration from this article: https://sound-au.com/articles/sinewave.htm#s44

Just tried to simulate with and without C4, and there is no discernible difference. Re-reading said article, and scrutinizing the circuit, I can only assume that the cap is there to make it compatible with DC-biased feedback networks. Great tip, I will remove this. Maybe you need a couple of 6800µF bipolars?

Which is one of the difficulties of using JFETs as variable resistors, they don't have a wide variable range.  The useful range of Vds is the difference between Vgs and pinch-off; so as Vgs approaches pinch-off, it looks more and more like a symmetrical constant current source with a small resistive step near zero.  Or something like that.  So, high Vgs (near zero) is preferable, and Rds is best varied over a modest range like 1:3 or something like that.

You are right, but for this specific application, linearity is only required over a very limited range, or so I believe. It seems to do the job well anyway. What alternatives are there for variable resistors?

You'll have the same fundamental problem with the fixed time constants in the feedback path -- since your precision detector is discrete-time, so also should be the feedback network.  Use switched-capacitor filters!

Now there are no time constants in the feedback path except the ones arising from stray capacitances - or am I wrong?

/Richard

[salbayeng]

Sorry for jumping in late.
What did they do in the old days?, e.g. the HP200 https://people.ohio.edu/postr/bapix/HP200CD.htm
This seems to have 3 capacitors, so guessing it was phase shift rather than Wein, AGC probably with light bulb.

Distant memory from the late 70's is that we used lightbulbs for AGC and back to back zeners, normal operation being about a volt less than the zeners, zeners were only active when you changed ranges, back then 1% was low distortion, although you would generally do better with valves than transistors.

The FET as a control element works but is a bit asymettric, maybe two FETs in series , or a RF type dual gate FET.

[Kleinstein]

With only a single frequency, the amplitude control part can work with a rather small range and the FET should work with no problem. One has to compromis on the voltage seen by the Jfet.  With high votlage the FET gets nonlinear and this can get through to the output. With to little votlage the control range gets small and the osciallator must be trimmed quite well to be just at the right gain.

With a variable frequency there is naturally more control range needed, as the the variabel capacitors / resistors may not be that accurate. So one may have to compromise here and look for good matching in the frequency setting.
In addition the AGC control loop also changes gain with frequency. So one may have to also change C5/R6 depending on the frequency - with a low frequency the loop must be slow and with a high frequency the control must be faster to still get a stable amplitude.

[richlooker]

Distant memory from the late 70's is that we used lightbulbs for AGC and back to back zeners, normal operation being about a volt less than the zeners, zeners were only active when you changed ranges, back then 1% was low distortion, although you would generally do better with valves than transistors.

The problem with light bulbs and thermistors is that they have a time constant that will introduce nonlinearities at low frequencies. I aim for low distortion down to 10Hz, so these are out of the question. And I regard 1% as HIGH distortion When it comes to zeners, I am skeptical as to whether they are "only active when you change ranges" - without active and continuous feedback, I don't see how you can keep gain at the correct level across different frequencies.

The FET as a control element works but is a bit asymettric, maybe two FETs in series , or a RF type dual gate FET.

With only a single frequency, the amplitude control part can work with a rather small range and the FET should work with no problem. One has to compromis on the voltage seen by the Jfet.  With high votlage the FET gets nonlinear and this can get through to the output. With to little votlage the control range gets small and the osciallator must be trimmed quite well to be just at the right gain.
With a variable frequency there is naturally more control range needed, as the the variabel capacitors / resistors may not be that accurate. So one may have to compromise here and look for good matching in the frequency setting.

I have made the voltage seen by the JFET as low as possible, while still having enough control range. The control range requirements are reduced through the use of high-speed opamps and switched 1% capacitors and resistors - no variable resistors here. The effect of JFET channel width modulation from the AC is minimised by ensuring that gate sees exactly 1/2 of the AC voltage applied to drain.

In addition the AGC control loop also changes gain with frequency. So one may have to also change C5/R6 depending on the frequency - with a low frequency the loop must be slow and with a high frequency the control must be faster to still get a stable amplitude.

The AGC control loop with the sample&hold peak detector does not change with frequency. The integrating element in the diagram - C5/R6 - is there to enable simulation of the circuit; Tina-TI chokes on the complete oscillator with S&H peak detector.

[richlooker]

A little simulation at 100kHz, just to illustrate the operating conditions for the JFET and my hypothesis that it introduces extremely little distortion.

Here are all the voltages, overlaid, with a calculated trace Vdist = (Vd/2 - Vg + Vfb/2) - this will be zero as long as AC at gate is exactly half the AC at drain, in practice it's in the ~1mV range.



Vout, Vd and Vg on separate scales - peak-to-peak 9.47V, 206.5mV and 104.9mV, repsectively.

[T3sl4co1l]

You are right, but for this specific application, linearity is only required over a very limited range, or so I believe. It seems to do the job well anyway. What alternatives are there for variable resistors?

Well, like I said, they're fine over a modest range, just a matter of biasing them there.  Which is just choice of R4/R5.  Hm, probably worth making one of those a trimmer, with calibration being, getting Vg near, but just below, 0V for all ranges.

Like, the simulated Vg ~ -0.7V should be fine, I expect Vpo isn't exactly -0.8V so the 0.1V drain swing is a small fraction of available range, and linearity will be good.  (Easy enough to confirm in the simulation, just plot i_d.)

If you can't avoid that on all ranges, then you aren't getting the full value of the intended variable resistance.  A nonlinear resistance might as well be a pair of diodes/zeners on R3.

Now there are no time constants in the feedback path except the ones arising from stray capacitances - or am I wrong?

I mean C5-R6, granted that's just for sim, but also to add a cap in series with R8 to get asymptotic settling.

If you're okay with the fixed gain solution, that's fine, but it won't be as stable.

Hmm, what kind of amplitude stability would be desirable anyway, say if Vg varies from -3..0V, then an error amp gain of 10 gives an input span of 0.3V, which is, well, 10% stability out of a 3V peak amplitude for example.  Maybe that would be good enough?

Tim

[richlooker]

AFter endless experimentation, I have found that it's really difficult to find an operating point for the JFET where I get oscillation (and not saturation) across the entire frequency range. Then I thought, you know what, this is supposed to be an experimental device anyway, so why not make the relevant controls available on the front panel?

This is my current concept for the front panel; the actual knobs laid out on a printout. I have not figured out how I can get the text/markings printed on the front plate. Any tips?