The discussing started with a variable audio oscillator...
It did indeed. And, as the name of the thread indicates, I want to solve it with a wien bridge oscillator. Furthermore, to use a JFET as the AGC element.
Using a fast microcontroller, you could read a 20 or 24bit sine table...
I work with digital stuff for a living. Analog nerding is my hobby. Microcontrollers and DDS are boring and devoid of soul. I find sophisticated analog solutions intriguing, elegant and sexy
Design goals:
- 11Hz-100kHz frequency range in four switchable decades
- Fixed/discrete frequencies, 26 per decade, per 26-position rotary switch (derived from requirement 1: I want immediate and precise frequency selection; dual-ganged pots won't do; and 2: I have this switch and want to use it )
- Super-fast settling time at frequency change, no amplitude wobble
- +12dBu / 3.1V RMS output & 11-step attenuator 0db - -60dB
- THD < 0.01% 100Hz-10kHz
- Learn a lot & have fun
- Make an awesome looking and practically usable device
For simplicity, I have kept the frequency at 1kHz while chasing the lowest possible THD. I expect THD to increase slightly towards higher frequencies, and probably a bit more as the frequency approaches 10Hz.
There is still one unsolved challenge; the aforementioned "gate charge transfer" artifact induced by the gating/sampling pulse. I cant't show a scope trace of this, as my scope just died, but simulation shows the exact same sharp "bump" on the sampled voltage. Unfiltered, this gets through to the JFET gate and causes a significant increase of 2nd harmonic distortion. I have - for now - tamed it with a low pass filter, but this will be optimal for a specific frequency, and as the oscillator frequency is lowered down towards the cutoff frequency, the filter itself will be a contributor to THD. I don't have the possibility to add more decks to the frequency range switch, but I could add another rotary switch to control the filter cutoff frequency.
In the article that inspired the start of my project: (
https://sound-au.com/project174.htm)
"Small 10µs pulses appearing on the AGC line are due to 'gate charge transfer' in the sampling switch, but again this is not an issue because thankfully the LDR is too slow to see them."
No problem with an LDR, but a problem for JFET stabilization. I would like to understand what this phenomenon really is, and how it's avoided/compensated in precision S&H circuits.
A 10ms simulation of the sample&hold circuit with 1kHz input:
And zoomed in to the problem area; as the gating pulse drives the gate of the J110 sampling switch high, a 23mV bump appears on the sampled voltage. The low pass filter tames it quite OK, but it smears the pulse out as a slow wobble, which may lead to problems as the oscillator frequency (or 2nd or 3rd harmonic) approaches the filter cutoff frequency.