Wien Bridge project

[Kleinstein]

In the simple circuit with a constant resistor from the source, one would also change the voltage on the DUT when changing the resistance. So at a higher fraction of R_on the test would be at a higher voltage and thus naturally more nonlinear.
For the application one more needs a certain level of voltage at the FET to have enough control range. So a fair comparison would be with changing the R_on of the fet, or comparing 2 fets in parallel to a single FET.

With the divide by 2 and a relatively high pinch-off, the circuit may not reach the fully off state in the practical circuit, but this is just a limit of the supply / circuit.

[richlooker]

In the simple circuit with a constant resistor from the source, one would also change the voltage on the DUT when changing the resistance. So at a higher fraction of R_on the test would be at a higher voltage and thus naturally more nonlinear. For the application one more needs a certain level of voltage at the FET to have enough control range. So a fair comparison would be with changing the R_on of the fet, or comparing 2 fets in parallel to a single FET.

Thanks for pointing that out; how about this circuit, where i can plot Vgs and Id with different, constant Vds settings? With no series resistor, I'll have to rely on the AC current accuracy of my Fluke 287, though. The 500µA range specification: Resolution 0.01µA, accuracy 0.6% + 20. The internal resistance is not stated, but I assume it's negligible.



Richard

[Kleinstein]

For chcing linearity it is not enough to measure the current with a DMM. The DMM can not distinguish between the excitation and the harmonics.

I would more consider a test with a kind of inverting amplifier, where the FET is the input resistor. The ouput would be inverting and one can thus easy subtract the approximate driving signal with just 2 resistors.


The resistor R9 would be chosen to the restance value to test, so maybe switchable to a few values of interest.
RV1 sets the DC gate level (some -10 V to -2 V) and would be adjusted to get low / minimal signal at the output.
RV2 (some 1 K) is for adjusting the symmetry of the JFET to trim the 2nd harmonic. To be fair with a single setting for the DUT.

The ouput should mainly give half the harmonic contend, with the excitation suppressed depending on how good the gate voltage is set.

[richlooker]

It's been a while since I worked on this project. That's how it is when you have too many projects 

I have modified the sample&hold peak detector a bit; originally I used schottky diodes, but the reverse leakage current of these proved problematic as I also made the hold capacitors smaller to reduce the current required to charge them - plain old 1N4148 does the job better, and the drop is compensated in the output buffer stage. Also added a circuit to detect a stalled oscillator - which may happen when changing frequency - as without this, the peak detector will continue to hold the last peak, and the oscillator will not start again. Lastly; a Sallen-Key 2nd order low pass filter on the output, to tame the little peak from the sampling pulse (explained at sound-au.com as "gate charge transfer"; not a problem for optocoupler stabilization, but with JFET stabilization it modulates Rds and contributes to THD)

Also done some modifications in the oscillator itself; it needs extremely low input leakage current to avoid interfering with the positive feedback network, but also high current / low impedance output to drive said network without lag or sag. A TL072 with the output buffered by an LM6172 fits the bill. The 50% feedback from drain to gate of the AGC JFET is isolated from the DC gate bias through a TL072 configured as a differential stage.

[richlooker]

The complete circuit breadboarded and under test.



The audio interface I used earlier (Propellerhead Balance) has developed a lot of noise and THD contribution, so I had to use the even older but still better NI Audio Kontrol 1.



As reference I am using my Tektronix ASG 100 audio signal oscillator.



Quite happy with the results now. Right/red curve is DUT, left/blue is ASG 100. I am obviously operating close to the limits of the audio interface, as 96 kHz sampling works best; going either up or down in sampling frequency produces poorer results. The specified THD for the Audio Kontrol 1 is 0.003%, so this makes sense. The DUT is quite sensitive to any touch, THD jumps up and down just by slightly moving decoupling capacitors, -88.1dB / 0.0039% is the best I can get with this setup, but I believe better than -90dB should be obtainable with careful PCB layout, placing ceramic & electrolytic decoupling capacitors close to the opamps and comparators, and by proper shielding.

[RoGeorge]

That's one of the most elaborated! 

[Messtechniker]

With Audio Tester it is - among other math - possible to subtract two curves; i.e. measured curve minus loopback curve, for example. See help file.

[Datman]

Experimenting is good, but you should also experiment various solutions and chose the best and simplest one! Try with an Arduino Nano and a cheap DDS AD9833 module from Aliexpress or Ebay: start by copying a simple project on the net, then study it, understand how it works and make it how you like. Arduino forum is very useful for learning  programming.

[RoGeorge]

The struggle in this topic was to get the lowest possible distortions at 1kHz.
By its datasheet, AD9833's distortions are about 100 times higher than this.

[Datman]

The discussing started with a variable audio oscillator...

[Datman]

Using a fast microcontroller, you could read a 20 or 24bit sine table...

[richlooker]

The discussing started with a variable audio oscillator...

It did indeed. And, as the name of the thread indicates, I want to solve it with a wien bridge oscillator. Furthermore, to use a JFET as the AGC element.

Using a fast microcontroller, you could read a 20 or 24bit sine table...

I work with digital stuff for a living. Analog nerding is my hobby. Microcontrollers and DDS are boring and devoid of soul. I find sophisticated analog solutions intriguing, elegant and sexy

Design goals:

• 11Hz-100kHz frequency range in four switchable decades
• Fixed/discrete frequencies, 26 per decade, per 26-position rotary switch (derived from requirement 1: I want immediate and precise frequency selection; dual-ganged pots won't do; and 2: I have this switch and want to use it )
• Super-fast settling time at frequency change, no amplitude wobble
• +12dBu / 3.1V RMS output & 11-step attenuator 0db - -60dB
• THD < 0.01% 100Hz-10kHz
• Learn a lot & have fun
• Make an awesome looking and practically usable device

For simplicity, I have kept the frequency at 1kHz while chasing the lowest possible THD. I expect THD to increase slightly towards higher frequencies, and probably a bit more as the frequency approaches 10Hz.

There is still one unsolved challenge; the aforementioned "gate charge transfer" artifact induced by the gating/sampling pulse. I cant't show a scope trace of this, as my scope just died, but simulation shows the exact same sharp "bump" on the sampled voltage. Unfiltered, this gets through to the JFET gate and causes a significant increase of 2nd harmonic distortion. I have - for now - tamed it with a low pass filter, but this will be optimal for a specific frequency, and as the oscillator frequency is lowered down towards the cutoff frequency, the filter itself will be a contributor to THD. I don't have the possibility to add more decks to the frequency range switch, but I could add another rotary switch to control the filter cutoff frequency.

In the article that inspired the start of my project: (https://sound-au.com/project174.htm)

"Small 10µs pulses appearing on the AGC line are due to 'gate charge transfer' in the sampling switch, but again this is not an issue because thankfully the LDR is too slow to see them."

No problem with an LDR, but a problem for JFET stabilization. I would like to understand what this phenomenon really is, and how it's avoided/compensated in precision S&H circuits.

A 10ms simulation of the sample&hold circuit with 1kHz input:



And zoomed in to the problem area; as the gating pulse drives the gate of the J110 sampling switch high, a 23mV bump appears on the sampled voltage. The low pass filter tames it quite OK, but it smears the pulse out as a slow wobble, which may lead to problems as the oscillator frequency (or 2nd or 3rd harmonic) approaches the filter cutoff frequency.

[Kleinstein]

The circuit uses the JFETs as switches in an unusual (wrong) way. When on the gat voltage should be at the signal voltage, not much higher. So the resistors should ideally go to a buffered signal that is switched and not the +Vcc.  This should reduce the switching spike quite a bit.
Another shouce of some switching spike is the gate capacitance. Ideally one would compensate with an opposite moving signal and a small capacitor to an opposing spike.
One could reduce the spike by using smaller / lower capacitance JFETs. The J110 noted in the plan is rather high capacitance. Something like J202 or J112 would be lower capacitance, though also higher on resistance.

[RoGeorge]

There is still one unsolved challenge; the aforementioned "gate charge transfer" artifact induced by the gating/sampling pulse. I cant't show a scope trace of this, as my scope just died, but simulation shows the exact same sharp "bump" on the sampled voltage. Unfiltered, this gets through to the JFET gate and causes a significant increase of 2nd harmonic distortion.

2nd harmonics means something that affect differently the upper vs the lower half semialternance of the waveform.  Maybe if you sample for both the positive and the negative peaks, then the influence of the sampling circuit will be symmetric, and thus less distortion of the 2nd harmonic type, plus the amplitude control might react even faster if the reading is on both the negative and the positive peaks of the waveform (instead of sampling only on the positive peak).

[richlooker]

The circuit uses the JFETs as switches in an unusual (wrong) way. When on the gat voltage should be at the signal voltage, not much higher. So the resistors should ideally go to a buffered signal that is switched and not the +Vcc.  This should reduce the switching spike quite a bit.
Another shouce of some switching spike is the gate capacitance. Ideally one would compensate with an opposite moving signal and a small capacitor to an opposing spike.
One could reduce the spike by using smaller / lower capacitance JFETs. The J110 noted in the plan is rather high capacitance. Something like J202 or J112 would be lower capacitance, though also higher on resistance.

I tried referencing the output of the pulse-generating comparator to the peak voltage through a buffer. Not much difference; still a bump at a little less than 20mV.

[PCB.Wiz]

• Fixed/discrete frequencies, 26 per decade, per 26-position rotary switch (derived from requirement
    1: I want immediate and precise frequency selection; dual-ganged pots won't do; and
    2: I have this switch and want to use it )

Hehe, I like that sort of requirement 

It also means you avoid the issues of pot tracking, and can use precision / matched resistors.
Precision caps would be interesting...

There is still one unsolved challenge; the aforementioned "gate charge transfer" artifact induced by the gating/sampling pulse. I cant't show a scope trace of this, as my scope just died, but simulation shows the exact same sharp "bump" on the sampled voltage. Unfiltered, this gets through to the JFET gate and causes a significant increase of 2nd harmonic distortion. I have - for now - tamed it with a low pass filter, but this will be optimal for a specific frequency, and as the oscillator frequency is lowered down towards the cutoff frequency, the filter itself will be a contributor to THD. I don't have the possibility to add more decks to the frequency range switch, but I could add another rotary switch to control the filter cutoff frequency.

You can also filter using pulse timing, but that adds more parts.
PLLs can have similar impulse problems, where a narrow pulse decides the information, but you want a smooth control.

They add a second sample and hold, that is disabled at and just after the impulse time, and enabled during the hold time.
That removes the bulk of the impulse, and you filter the rest.

[richlooker]

There is still one unsolved challenge; the aforementioned "gate charge transfer" artifact induced by the gating/sampling pulse. I cant't show a scope trace of this, as my scope just died, but simulation shows the exact same sharp "bump" on the sampled voltage. Unfiltered, this gets through to the JFET gate and causes a significant increase of 2nd harmonic distortion.

2nd harmonics means something that affect differently the upper vs the lower half semialternance of the waveform.  Maybe if you sample for both the positive and the negative peaks, then the influence of the sampling circuit will be symmetric, and thus less distortion of the 2nd harmonic type, plus the amplitude control might react even faster if the reading is on both the negative and the positive peaks of the waveform (instead of sampling only on the positive peak).

Interesting idea, but I am inclined to shy away from the complexity of sampling the negative peaks also. It means duplicating at least 2/3rd of the circuit, finding a reliable way of negating the sampled negative values, and compensating for any DC offset that will otherwise lead to a square wave superimposed upon the output. But your answer is also pointing me towards another potential improvement: Timing capacitors in the oscillator feedback network. I have relied on 1% tolerances with no further matching, but maybe I should buy eg. 10 of each value required and pick the pairs that matches most closely.

[Kleinstein]

The filter / compensation in the AGC part does not provide a lot of low pass filtering. There is the 2nd order active LP filter for the V_out signal, but the regulator is a simple proportional one.
The more normal way is to have a more PI type regulator and thus a kind of integrator (capacitor in series to R13) to control the JFET for the amplitude regulation. This way the pulse at Vput may have less effect.

20 mV is about the order of magnitide expected for the gate charge of T2 and the 10 nF hold capacitor.  A smaller JFET for T2 could improve things.

[richlooker]

You can also filter using pulse timing, but that adds more parts.
PLLs can have similar impulse problems, where a narrow pulse decides the information, but you want a smooth control.

They add a second sample and hold, that is disabled at and just after the impulse time, and enabled during the hold time.
That removes the bulk of the impulse, and you filter the rest.

I found this paper: https://www.uio.no/studier/emner/matnat/ifi/INF4420/v11/undervisningsmateriale/INF4420_V11_0208_2.pdf

Is this what you are suggesting? And would MOSFET's be a better choice than JFET's?

[PCB.Wiz]

Is this what you are suggesting?

Yes, the first drawing, has series anti-phased switches (missing is an actual second hold cap, after M2 )

And would MOSFET's be a better choice than JFET's?

You would need to check the linear regions.

Many of the JFET info's on the web are just plain wrong.

This is one of the better ones
https://www.allaboutcircuits.com/textbook/semiconductors/chpt-5/active-mode-operation-jfet/
tho here they do not plot into the 3rd quadrant.

This is the bit that matters :
A contrast of the JFET’s characteristic curves against the curves for a bipolar transistor reveals a notable difference: the linear (straight) portion of each curve’s non-horizontal area is surprisingly long compared to the respective portions of a BJT’s characteristic curves:

ie you want a device with 'longest straight parts of the curves', and with a useful resistance operate region.

MOSFETS tend to be lower on resistance, (aka 2N7002), but there are modern high voltage mosfets, that could be worth exploring.
eg I find a AO3160 that is 600V 300 ohms tho the curves stop before they show your AGC operating region, so you would need to curve-trace those.

JFET optocouplers are another control option ?

The other control element you could look at, is the Operational Transconductance Amplifier ?  ( NE5517, LM13700, LT1228, LT1256  ... )
These have a low linear input region (sub 100mV) but they drive a multiplied current output that is a fraction of the active current, as it's just needed for gain-variation correction.

Addit : I also found this from onSemi    AN-6603  A Linear Gain Controlled Amplifier, which shows small injection used from drain into gate, to lower distortion.
https://www.onsemi.cn/pub/collateral/an-6603cn.pdf

[David Hess]

The other control element you could look at, is the Operational Transconductance Amplifier ?  ( NE5517, LM13700, LT1228, LT1256  ... )
These have a low linear input region (sub 100mV) but they drive a multiplied current output that is a fraction of the active current.

The Linear Technology part-per-billion Wien bridge oscillator used the LT1228.  This is the design to use for *testing* 24 bit ADCs.

[jonpaul]

See the papers on low THD, audio gen, esp Hewlett and Packard 1930s, Jim Williams, and Audio Rpecision.

The variable element must be totaly reisitive and isolated from the contl loop, only a CdS photoisolator and thermistor or incandescent lamp have suceeded.

The JFET, work but do not give a great THD over the freq band.

J

[PCB.Wiz]

See the papers on low THD, audio gen, esp Hewlett and Packard 1930s, Jim Williams, and Audio Rpecision.

The variable element must be totaly reisitive and isolated from the contl loop, only a CdS photoisolator and thermistor or incandescent lamp have suceeded.

Not quite.
The variable element must be linear, it does not need to be resistive. (see the very low distortion LT design mentioned above using LT1228 )
It also helps if the variable element is nulled, so it manages only unbalance, (as per LT design) as that can slash the distortion contribution.

That means fixed frequency oscillators can have better specs, than ganged-pot variable designs.

[Kleinstein]

The charge inection compensation is what is wanted for the sampling pulse. Discrete MOSFETs are a bit tricky to use, as there are very few with a separate substrate connection. So the choice is mainly between JFETs and CMOS switch chips (e.g. CD4066, DG211). As the pulse is essentially fixed (fixed voltage when stable) and can be reduced with a smaller JFET, one may not need the full program.

[richlooker]

The charge inection compensation is what is wanted for the sampling pulse. Discrete MOSFETs are a bit tricky to use, as there are very few with a separate substrate connection. So the choice is mainly between JFETs and CMOS switch chips (e.g. CD4066, DG211). As the pulse is essentially fixed (fixed voltage when stable) and can be reduced with a smaller JFET, one may not need the full program.

Thanks a lot for the "smaller JFET" tip

Assuming the TINA-TI models are representative, this did wonders. With J112, the clock feedthrough was reduced (from approx 23mV with J110) to less than 10mV. The ripple is also more rounded, so it's easier to filter:



As for J202, the pulse was further reduced to less than 5mV, as is rounded even more, but now Rds(on) is too high, so almost 10 samples is required before the output stabilizes (not shown in this trace). Not a problem with high frequencies, but more of a problem in the 10-50 Hz area: