High quality audio opamp (discrete), under development.

[Kokoriantz]

I added a current mirror instead of ccs, to make the output in push pull and adjusted for +/-6v to get 0.00015% THD at 2vrms. It remains the same with +/-15v.

[Kokoriantz]

The above circuit had serious saturation trouble, resolved by 2 diodes and a ccs.
It didn't need precise current mirror to work in push pull.
The circuit now for 2vrms, exhibits 0.0002% with +/-5v and 0.00007% with +/-15v. It may be possible to run it with +/-40v to be used as IPS+VAS stage.

[MariuszD]

Your amplifier has a high output impedance, which means its parameters will depend on the load. Have you checked the requirements for the FDNR filter?

[Kokoriantz]

What makes you think the output is high Z. The feedback decreases it.
It is 0.2 ohms flat to 1Mhz.

[mawyatt]

This doesn't make sense. The unity gain -3dB BW appears to be ~30MHz, so at 3MHz the Open Loop Gain is 20dB higher, and 300KHz another 20dB and at 30KHz it's 60dB higher. This somewhat agrees with your output Z plot, showing a break at 30~40kHz. So the Open Loop Gain isn't sufficient to drive the output Z lower than 0.2Ω below 30~40kHz.

With an Open Loop 1st order gain break at 30~40KHz, then the output Z at 400KHz should be ~2Ω, and at 4MHz ~20Ω, or ~5Ω at 1MHz without any additional impedances involved.

Best

[MT4S301]

Output resistive load decreases gain of 2nd stage (from gm*ro to gm*RL) and its closed-loop response will never be the same.
Things get worse since your first stage is a low-gain resistor loaded JFET stage.

[Kokoriantz]

See the output Z to 1Mhz.

[Kokoriantz]

The LTspice working version.

[Kokoriantz]

I think I reached to a good model to prototype. I still have the saturation problem that needs to limit the input to Vcc-1.5v so that the jfet doesn't reach D-S to 0v.
I over stabilized to get easier prototyping.

[David Hess]

I couldn't find the circuit by John Addis,
https://w140.com/tekwiki/wiki/John_Addis.

In context John Addis was discussing how to improve on the alpha of an emitter follower, shown below.

In a discrete version, I would test replacing Q3 in 14-8c with a JFET to lower the collector load, and then adding local feedback around Q4 by changing it to a PNP and moving it to the drain side as shown in many two transistor JFET followers, also shown below.  This is common in oscilloscope vertical inputs where the output impedance of a JFET follower is too high to drive a 50 ohm load.  John Addis was designing an IC so did not have this option.

[MariuszD]

What makes you think the output is high Z. The feedback decreases it.
It is 0.2 ohms flat to 1Mhz.

I know that feedback reduces output resistance. But a filter is not a buffer. Filters often impose additional requirements. Since your amplifier is going to work in the filter, you should check early whether it will work correctly in the filter.

[Kokoriantz]

Saturation problem solved by adding 4 diodes.
The CFP jfet+bjt is good to get high gm by using low gm jfet for low input capacitance. The 2sk209 for audio is sufficient as stand alone LTP.
I will try with the FNDR circuit.

[Kokoriantz]

I started the miniature PCB and I realized that The circuit has too many components to fit. The low dissipating transistors are replaced by dual 2n3904 and 3906 in miniature sot323, and diodes are made of them for size and thermal matching. The 2sk209 has dual in sot323 package as 2sk2145 for $1.5 non matched, Toshiba being only manufacturer and it will discontinue the 2sk209 probably the 2145 too.
The CCS low currents are also dual sot323, the 10ma and the output are sot23.
The circuit bellow is the simpler one with 0.0002% @2vrms for 6v and 15v. I will be happy with this if I can fit as Sparkos size.

[Kokoriantz]

A PCB size view. I may be use a single pcb with each channel on the either side, for lower mounting cost.

[Kokoriantz]

I made the two channels on seperate boards to be sandwiched with the components outward with 2 layer pcb. To get lower cost of populating, I made the component sides on the same top layer. The pair measure less than 40x20mm so that on standard 100x100mm it can have 12 pairs per board. I need to find a way to convince the JLCPCB that it is one circuit in multiple examples.
The kicad file is bellow.
I'll post the LTspice later.
I don't know how to draw a groove on kicad so that the PCB can be separated by hand.