The long awaited continuation!
Suppose we generate a PWM square wave, with duty cycle reasonably proportional to an input voltage. If we filter this (removing the AC components, leaving just the average DC value), we get the original voltage back ... but not exactly, because PWM is a digital function, and digital signals are a matter of definition. Namely, the '1' and '0' voltages are defined by what the logic puts out. So the output is actually proportional to the digital logic levels.
Hmm...
Suppose we use our digital PWM signal as one input to a one-bit DAC, and set the reference level of that DAC from another voltage. Ahah, now we have an output (after filtering) that's jointly proportional to two signals: a product!
(And yes, a "one bit DAC" is not a useless concept -- semantically, we're translating from an abstract digital signal (which might have unstable voltage levels, ratty rising and falling edges, lots of noise, etc.), to an analog signal that's supposed to be precise and stable. For many purposes, a CMOS logic gate actually does a fine job of this, which is seen from time to time. We can't use a logic gate here though, because of the voltage range required.)
Such a circuit might look like attached (see PDF). The top half is a ramp oscillator (Fo = 191kHz) and PWM comparator. (A 555 timer could be used for the oscillator just as well, perhaps saving a few resistors, but the current source is important, otherwise you get a sloppy waveform, and poor linearity along one axis. More on that later. This entire section could be replaced by an LT TimerBlox IC, but wouldn't handle the supply voltage, and would still cost more. Although it would save considerable board area.)
The bottom half buffers the input, drives a MOSFET pair, then filters it (3rd order ~Butterworth, Fc = 3.6kHz) to give a stable "DC" output. The magic part is the MOSFET pair, which acts as a one-bit DAC, switching between the buffered signal, and the ground reference (VGND comes from a voltage divider, so is about 6V; all the input and output measurements are relative to this net). As long as the digital voltage swing is much greater than the reference voltages, this works well. The analog voltages are 6-9V (relative to GND), and the digital signal is 0.4V/11.6V, so this gives plenty of headroom to turn on the MOSFETs.
The main drawback, as shown, is the considerable capacitance of these transistors. This necessitates R9-C2 to mitigate the charge injection (otherwise there is a pronounced spike in the waveform, and much more error, at low duty cycles). Very much smaller devices should be used, preferably a monolithic analog switch, like 1/3 CD4066.
Results:
The bi-linearity is pretty good. Modeling the data as a 2nd order bi-variate polynomial, the error is:
RMS 1.03% FS
Peak 1.64% FS
Setting the quadratic terms to zero (i.e., only linear offset/gain corrections required to get a pure product result), the errors are,
RMS 1.15% FS
Peak 1.67% FS
Some plots are provided for flavor. The first simply shows the data series; this isn't very illustrative, aside from seeing the nonzero intercept. The second shows three "slices" through the data, along the Vin1 = const axis, Vin2 = const, and along Vin1 = Vin2 (which is, ideally, the simple product). The third shows the "error bars" as a function of coordinate.
You'll notice the error seems to be biased along vertical columns: this suggests the Vin1 port has worse error. Which seems to suggest an error in the voltage-to-PWM conversion. There would be a pronounced curve here (something like flexing a sheet) if I had used an RC timer instead of the current source ramp generator. Probably, contributing factors are capacitance variation (Y5P disc cap, transistor Ccb), current source stability (should be pretty good actually), comparator speed and output voltage stability, and so on.
Tim
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