UVLO Latching Circuit

[hsquared]

I am designing a LM5176 buck-boost. I ran into an issue where the pre-bias isn't working as smoothly as I had hoped. (If Vin turns on while Vout is still high for whatever reason, the controller tries to reduce Vout by driving negative current).

I wanted to overcome this by just creating a latching circuit that disables the controller until Vout falls low enough.

I created this BJT circuit that I believe works. I was wondering what this type of "design" is. Is there a name for this type of design or methodology? And is this a good method to solve this problem?

I created a table to remind myself what the circuit should do.
Vin, Vout, (EN/UVLO)', EN/UVLO
H,   L,    X,          Vin    - Vin turned on, Vout is low, EN/UVLO should track Vin
L,   H,    X,          L       - Vin low, Vout still high, EN/UVLO should latch low
L,   L,    X,          Vin    - Vin low, Vout fallen, EN/UVLO should track Vin
H,   H,   Vin/H,   Vin     - Vin and EN/UVLO were high, Vout turned on, EN/UVLO should track Vin
H,   H,    L,          L      - Vin high, Vout high but EN/UVLO was latched low, so EN/UVLO should continue being latched low