Sigma Delta ADC Design

[iMo]

While watching the achievements in the Multislope design thread I've tried with a simple Sigma Delta ADC in hardware, no simulation this time ..

With UPduino v1 and the Lattice's "Simple Sigma Delta ADC Design" whitepaper I wired an 18bit ADC, with 22bit accumulator and 4 LPF_depth_bits I get 1 measurement in 2.8seconds. Internal FPGA's 24MHz RC oscillator is used.

Link to the SD ADC paper. You may download verilog source from that site too.

The FPGA's DDR input primitive for the input stream is used. The FPGA's LVDS comparator could be selected provided you can source the IO bank with 2.5V (UPduino is hardwired to 3.3V).

The max PWM frequency I can see is around 4MHz.

The schematics is pretty simple, see below. The 5V comes from a phone charger, 3.3V comes from BluePill (used as voltage regulator only).

UPduino and LM311 are put on a solderless breadboard. Serial in/out comes from the iCE40 FPGA via HC-05 into the PC.

Teraterm is used for logging data and communication with a built-in mcu, TimeLab for visualization of data.

No special voltage regulators or references are used.

The SD ADC's output data are from aprox 7600 to 262000 with the 10k 10t pot.

So far I get "5.5digits" where the last digit is jumping +/- 1 typically when the pot is wired to 3V3 - that is the ref voltage for the PWM as well, therefore the "stability" is expected.

When the guys finalize the multislope we may measure the INL and stability of this simple SD ADC..   

Update: updated the schematics and measurements.

Code: [Select]

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[iMo]

First measurement - a TL431 @2.5mA instead of the pot.

[Kleinstein]

I think one of the problems of the simple circuit is that one directly gets the noise (including the 1/f part) and drift from the LM311. AFAIK there are not much noise specs on the comparator, but I am afraid the noise would not be very low, like what one would expect from a low noise op. The LM311 also has quite some bias current, that can be a factor.

The effective reference is the 3.3 V supply for the PWM signal - so a rather low level, that makes the noise rather important. There are probably better 3.3 V regulators than the blue pill  .

[iMo]

The PWM would require a different approach - there will be a buffer made of a single gate (5 pin smd) powered by an LT1021B-5.
Also a canned 3.3V xtal oscillator, and PLL (there is one in the fpga) say 80MHz feeding the SD ADC clock.
Also the comparator will be different, sure
Then we need a better filters in the dsp chain as well. Etc. Etc.

PS: so far I've been messing with fp, after a "calibration" my UPduino is finally printing TL431's voltage in the new Volt

2.54616
2.54617
2.54613
2.54600
2.54598
2.54581
2.54578
2.54578
2.54559

FYI - this is how the raw 18bit data (2x16b) is read out off the SDADC and then printed out as the voltage 

: sdadc 700 io@ 701 io@ ; 
: sdf sdadc d>f ;
: sdvf f# 0.007069e f# 1.3e-5 sdf f* f+ f. ;

[Wimberleytech]

Cute!

[moffy]

Very nicely done. I am a bit surprised that you are only getting 1 sample every 2.8 seconds.

[Wimberleytech]

Very nicely done. I am a bit surprised that you are only getting 1 sample every 2.8 seconds.

Single integrator needs very high OSR to get decent resolution.

[moffy]

That makes sense. I've been playing with a second order integrator and 10MHz sample frequency and getting 10kHz BW with 16 bit resolution.

[Kalvin]

I wonder whether using this Faster PWM DAC topology would improve the performance, as this topology will eliminate the ripple associated with the traditional PWM DACs:

https://www.edn.com/design/analog/4460665/Fast-PWM-DAC-has-no-ripple

[Wimberleytech]

I wonder whether using this Faster PWM DAC topology would improve the performance, as this topology will eliminate the ripple associated with the traditional PWM DACs:

https://www.edn.com/design/analog/4460665/Fast-PWM-DAC-has-no-ripple

The sampling block following the comparator in the Lattice article effectively does what is described in this edn article.

[iMo]

Another experiment - the "network topology" as Lattice calls it. See below the schematics.

With Vref=3.3V / 2  (thus the PWM and the comparator share the same source for Vref=Vccio/2) and R1=R2 the Vinp=0..3.3V maps to 0..FullScale_18bit.

See below the calibration table and formula (the Forth runs inside the UPduino).

Code: [Select]

: sdadc 700 io@ 701 io@ ;                                 \ read the raw data from the sdadc 2x16bit
: sdf sdadc d>f ;                                         \ read and convert int32 to float (48bits fp)
: sdvf f# 4.96897511e-3 f# 1.2578181e-5 sdf f* f+ ;       \ .. convert to Volts

The peak in the TL431 measurement with v2 (tl431 @2.5ma wired to the Vinp) comes from my writing this post (see above the shot with my setup) 

[iMo]

SD ADC v3 with a Second Order SD modulator based on TSP #32 blog.

Below a continual measurement with a stable run for ~3minutes, 1measurement in aprox 2.8secs.

####

PS: this particular kind of SD ADC (see above Lattice whitepaper) works such the 1bit bitstream from the Modulator (an integrator, comparator and a single FFlop) is accumulated in ACC (ie 19bit) while it adds the actual level of the bitstream to ACC on each modulator's clock (ie. 1.5MHz). To count 19bits takes 2^19/1.5M=0.35secs therefore.

After that time the 19bit ADCsize data are passed into an LPF (and the ACC is reset to zero), in case of LPF=3 it takes 2^3 passes, thus a single measurement takes 0.35*8=2.8secs.

There is an option to have ACC>ADCsize, ie 22bit ACC and 19bit ADCsize, then it takes 2^(22-19) times longer to get a measurement (the larger ACC does averaging).

####

The UPduino with the Simple SD as above (19bits ADCsize, ACC=19, LPF=3, sampling clock=1.5MHz ).

Added the inverted signal from the 1bit FF sampler (Q and /Q outputs, 3.3V logic) fed into the second integrator.

SD reference voltage is the Vcc=3.3V of the FPGA.

All put on the solderless breadboard wired with jumping wires, voltages stabilized by 1117 and 7905.

Below is a 3minutes long measurement of an TL431 done under stable conditions (I hold my breath ), you may see how the last digits flips.
 
The data are the raw data coming directly from the SDADC, multiplied by -3.3V/(2^19). Not calibrated.

When the SD ADC data are available an interrupt is asserted and the main loop reads the data.
Forth running in the FPGA:

Code: [Select]

0 variable sdflag

: isdadc ( -- )                     \ ISR: INT_SD interrupt
   $bF intflag! $FF intflag!        \ ISR: clear the INT_SD flag
   1 sdflag !                       \ ISR: set SDADC data ready flag
   ;          

' isdadc 1 rshift $3BFC !           \ place isdadc ISR at INT_6 vector location

: sdadc 700 io@ 701 io@ ;           \ read SDADC raw data
: sdf sdadc d>f ;                   \ convert to float
: sdvf f# 6.2942504882e-6 sdf f* ;  \ make Volts, mult by 3.3/2^ADCsize

: testx BEGIN                       \ wait on a measurement, print result in Volts
        sdflag @ 0<>                \ is the SDADC flag set? Loop
        UNTIL
        sdvf f.  cr                 \ print Volts
        0 sdflag !                  \ reset SDADC flag
        ;
 
: test 0 do testx loop ;            \ do XXXX measurements

$40 intmask!                        \ enable isdadc interrupt
eint                                \ global int enable

7 set-precision                     \ we will print 7 digits
30000 test                          \ do make 30000 measurements

The STDEV is 11.5uV of that measurement.

[jaromir]

Your post from late May looks promising.
Any news on this topic?

[iMo]

Since then I tried with sinc3 filters but the results are rather poor.
The sinc3 filter code came from AD7402 DS, for example.

PS: One issue I can see with this design is its complexity (when you want something similar to the Multislope) tends to be pretty large. For example the Q and /Q signal levels have to be switched from +Vref=10V to -Vref=-10V, at around 1-2MHz.. And the resistors, capacitors and opamps with same quality as with Multislope.

[SiliconWizard]

I've never implemented a sigma-delta ADC, but I have implemented sigma-delta DACs. I got pretty good results using only linear interpolation for the oversampling stage. Sure that's not ideal, but it takes up a lot less area and can run much faster.