Electronics > Projects, Designs, and Technical Stuff
Wiring Harness Tester - Confused about Some Crucial Design Decisons
PsychedelicBreakfast:
Hi everyone,
I've discussed various aspects of my project on various forums over the web (Electronics Stackexchange etc.) but I'm sort of stuck on some aspects. I'd ask on Stackexchange, but I felt the topic lent itself more to discussion than to Q/A, hence my post.
I'm designing an electronic wiring harness tester for my employer. I have two CPLDs, one as a designated driving end (all pins are output) and another as an receiving end (all pins are input). The driving end CPLD is programmed to be a Serial In Parallel Out shift register and the receiving end is a Parallel In Serial Out shift register.
Let's assume all the wires in the harness are one-to-one i.e. no junctions. Let's also assume that there are only 8 wires. So, to test the first wire in the harness, the driving end register is loaded with 10000000. The receiving end also sees this and it all ends well. The driving end is then clocked and it reads 01000000. If the receiver also reads this, then that wire is OK. I'm sure you can see how this also works if a wire has a junction.
I should add that the speed of operation is very slow. The receiving end shift register is clocked out at just 62.5kHz. The driving end will, of course, be even slower as the MCU has to wait.
Here's where I've hit a road block:
1) If there is a short circuit between wire 2 and 3, then the output pins connected to pin 2 and 3 will "fight" each as one would force 3.3V (the active pin) and the other would force 0V (the inactive pin). I discussed this on Stackexchange and was given quite an elegant solution - instead of having 0 on the inactive pins, I should tri-state them and use a pull down on the other end.
This made sense to me but then I realized that suppose there's a junction with, say, 50 wires going out. Let's further suppose I have a pull down resistor of 5K. If this is the case (and it's quite common that it is so!), then the a single output pin on the CPLD needs to be output:
50 * 3.3/5000 = 33mA.
Unfortunately, my CPLDs pin are not strong to do so. The max. rating is just 25mA. The obvious solution at this stage is to just increase the resistance to, say, 47K. This will reduce the current to just 50 * 3.3/47K = 3.5mA. But this obviously results in a weaker pull down and I was warned that EMI could end up causing trouble for my circuit. The harness, particularly for trucks, can be quite long! Upto 10 meters in some cases. Do I need to worry about EMI effects if my frequency is just 62.5kHz?
2) I was recommend that instead of a pull down/up, I should add in a transistor. This will pull the current directly from the supply and the not from the pin, so that problem is solved in anycase. But I wish the solution was easy as this - the issue is that the harness can be large as 300 wires in some cases and my circuits needs to be able to test that.
This isn't as difficult to realize as it may seem - I can achieve it by just cascading 3 TQFP-144 CPLDs for the driving end and the same for the receiving end. But if I start putting a MOSFET on every IO trace, its going to make an extremely large board.
3) I do have a solution for this. But I just don't know if its a good solution. Instead of having a large massive PCB to test 300 wires, I should instead have a "main board" which consists of a single MCU, and two CPLDs. This would allow me to check 114 wires. If a bigger circuit is required, we connect a "daughter board" to the "main board".
This PCB would consist of two CPLDs which, when connected to the main board, are cascaded with the other two CPLDs to form a larger shift register. We could extend this approach for how many we desire. But is this a good solution to the problem? It's advantageous when it comes to costs. Most of the harnesses are small and can be tested with just the main board. Why get a such a large circuit manufactured when we're only gonna test small harnesses most of the time? And when its required to test a large harness, we can simply cascade the other smaller PCBs.
But I'm wondering if I'm "over-engineering" the problem here. If I don't need the transistor and can get away with a weaker pull up, then I feel thats a better approach. I can even reduce the frequency of the operation even further. It's not the limiting factor. I'm just after a reliable design (aren't we all?!) which is not influenced by EMI factors or other such issues.
Thank you for reading this massive post. I realize how long it is but felt I should give you guys full information on the subject. Also, I know I should probably have this discussion with my colleagues but unfortunately I'm the lone electronics engineering at the company :(.
Neilm:
To decide if EMI would be a problem, you would have to consult the relevant standard. I don't know if there would be one especially for this sort of application otherwise IEC61326( Electrical equipment for measurement, control and laboratory use - EMC requirements) would be worth consulting. While 62kHz might not be very fast, if the edges rise quickly you might have a problem. As it isn't very fast, you could add some capacitance to the line so it only changes slowly.
I would agree with the ideas from Stackexchange for doing the actual testing, although I would probably have them all pulled up then pull each one down using a transistor That way only one resistor would be conducting at a time and so less power would be used. You don't need a MOSFET for this just an ordinary transistor (BC817 for instance) would do. They are available in SOT23 form so are quite small.
One thing I would not do is directly put the CPLD onto the output, there exists the possibility that an ESD spike could damage the chip which would mean the whole device needs replacing. The transistor would would be a lot easier to fix and probably more robust. (This depends on the CPLD you are using, but I have had problems due to ESD in the past).
Neil
Simon:
I think you just need to bite the bullet and put as many I/O as you require without over designing. if the wire has junctions then you have 1 input and n outputs as each needs testing separately, I'm not sure why you are so concerned about pull ups/downs, why not just put a 1 or 0 on the wire straight from the mcu and let the other mcu or other device at the other end read that and let you know the result ? as for speed, well I don't know how complex the looms are but surely if you are afraid of EMI which should not be an isssue as you test one wire at a time then just reduce the frequency or rather the speed at which the wires are tested, even 1 second should be long enough to do a full test without high frequencies travelling down the wire.
PsychedelicBreakfast:
--- Quote from: Neilm on October 27, 2011, 05:55:44 pm ---To decide if EMI would be a problem, you would have to consult the relevant standard. I don't know if there would be one especially for this sort of application otherwise IEC61326( Electrical equipment for measurement, control and laboratory use - EMC requirements) would be worth consulting. While 62kHz might not be very fast, if the edges rise quickly you might have a problem. As it isn't very fast, you could add some capacitance to the line so it only changes slowly.
--- End quote ---
I should've added that transmitting EMI isn't a concern. The device isn't going to be sold on the market or anything. I'm concerned about "false negative" because this device is going to be used on wiring harnesses the company manufactures for quality assurance purposes.
--- Quote ---I would agree with the ideas from Stackexchange for doing the actual testing, although I would probably have them all pulled up then pull each one down using a transistor That way only one resistor would be conducting at a time and so less power would be used. You don't need a MOSFET for this just an ordinary transistor (BC817 for instance) would do. They are available in SOT23 form so are quite small.
One thing I would not do is directly put the CPLD onto the output, there exists the possibility that an ESD spike could damage the chip which would mean the whole device needs replacing. The transistor would would be a lot easier to fix and probably more robust. (This depends on the CPLD you are using, but I have had problems due to ESD in the past).
--- End quote ---
This is a great point. I understand that a transistor should be between the CPLD and the harness for protection but I'm having trouble visualizing how the transistor ought to be connected. Are you suggesting that I connect the harness onto the collector - with a resistor between Vcc and the collector pin? The output of the CPLD is then connected to the base of the transistor. The other end(s) of the harness is then directly connecting to the input pin of the receiving CPLD - and I assume that there is less chance of ESD damage at this end because of the high input impedance of an input pin. Am I correct so far?
Thank you for an excellent response, by the way. I really appreciate it.
PsychedelicBreakfast:
--- Quote from: Simon on October 27, 2011, 06:13:01 pm ---I think you just need to bite the bullet and put as many I/O as you require without over designing. if the wire has junctions then you have 1 input and n outputs as each needs testing separately, I'm not sure why you are so concerned about pull ups/downs, why not just put a 1 or 0 on the wire straight from the mcu and let the other mcu or other device at the other end read that and let you know the result ?
--- End quote ---
There is a problem with this approach. Think of the devices as simple 8 bit shift registers. Let's assume the wiring harness only consists of one-to-one wiring. When the Parallel Out shift register outputs 01000000 and receiving end will see 01000000. If however, there is a short between pin 1 and 2, the receiving end will see 11000000. This isn't a problem so far, but think of what is happening at the output pin 1 and pin 2. Pin 1 is trying to force 0V while pin 2 is trying to force 3.3V - I don't think this is a good approach. By using tri-state outputs with pull up/down resistors, I don't have to worry about this problem.
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