EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: shamooooot on April 07, 2022, 05:58:42 am
-
Hellos
I am working on designing a thyristor gate control board and I have the final output which I am not sure if it is a correct or not.
(https://i.ibb.co/7KR0D63/73FTA.png)
(The pulse transformer I have is 77202C instead 77205C, and R18 is 12.5ohm)
- Blue is the input to the 10ohm resistor connected to the gate of the 2N7000 transistor.
- Yellow is the output of the pulse transformer GG3 and K3.
(https://i.ibb.co/H4hcR7z/Whats-App-Image-2022-04-06-at-5-41-59-PM.jpg)
The thyristor I am looking to drive is S8006L.
-
That looks like a pretty small signal at 0.6V amplitude
What is the reason for using a transformer anyway? It doesn't look like you are using it for galvanic isolation or anything.
You can just shove 50mA right into the gate from the 5V rail using a PNP transistor if you just need to turn it on.
-
Why is the waveform so nasty?
Tim
-
What thyristor are you using?
How much current can the logic circuit, or MCU output source/sink?
The pulse transformer can be configured 2:1 by connecting two of the secondary windings in parallel. This will result in double the current through the thyristor's gate, so the primary drive current can be halved.
Refer to the application note linked below.
https://www.st.com/resource/en/application_note/cd00003863-triac-control-by-pulse-transformer-stmicroelectronics.pdf (https://www.st.com/resource/en/application_note/cd00003863-triac-control-by-pulse-transformer-stmicroelectronics.pdf)
-
When I have controlled SCR's I sent a burst of on pulses, closely together, to overcome any reluctance of the SCR to turn on, that way you are less likely to miss a cycle, they were however 1500V/2000A devices. I also would put a low value resistor across the output of the transformer/gate to try and prevent noise switching due to dv/dt.
Are you driving a thyristor gate, and is that the voltage waveform(yellow) across the gate? What is of more interest is the current pulse into the gate.
-
Very hard to understand that schematic
Suggest that you learn how to draw transformers schematic symbol or find,one,from vendors
Jon
-
Very hard to understand that schematic
Suggest that you learn how to draw transformers schematic symbol or find,one,from vendors
Jon
Indeed the symbol is a bit strange. It would be better represented as:
(https://www.eevblog.com/forum/projects/would-this-signal-be-sufficient-to-control-thyristors-gate/?action=dlattach;attach=1457431)
Datasheet:
https://www.mouser.com/datasheet/2/281/kmp_772-41255.pdf (https://www.mouser.com/datasheet/2/281/kmp_772-41255.pdf)
The pulse transformer can be configured 2:1 by connecting two of the secondary windings in parallel. This will result in double the current through the thyristor's gate, so the primary drive current can be halved.
Indeed. That is what I would try as well. After all, one of the secondaries is simply left aside.
Regardless, the application of the transformer itself seems quite overkill - no galvanic isolation at all...
-
In the OP diagram SECONDARY_2 is being used as a demag winding.
-
In the past I've used a 3:1 pulse transformer connected in series with a DC blocking capacitor and current limiting resistor. The 3:1 ratio was enough to boost the current to drive a sensitive gate TRIAC. I didn't have any problems with spurious triggering due to the inductance of the transformer, because the resistor did a good job of damping.
(https://www.eevblog.com/forum/projects/designing-a-triac-driver-from-scratch-(not-using-store-bought-stuff)/?action=dlattach;attach=1222085;image)
-
Note that TRIACs have a back-to-back diode characteristic between G and MT1, so the above circuit is excellent for triggering them: the secondary resistance shunts gate leakage (improving stability at high temperature I suppose, maybe somewhat improving dV/dt immunity too?), while the diode characteristic ensures full conduction for both phases of drive. You use a gated clock signal to trigger it: the continuous up-and-down ensures operation in quadrants 1 and 2 (load positive) or 3 and 4 (load negative), and keeping the pulses going during operation ensures minimal dropout in case conduction angle isn't as expected.
The uh, gate still carries some voltage drop when on, doesn't it? SCRs for sure, TRIACs I don't actually recall. So you might want a series gate resistor on that still, so that the secondary DCR isn't shorting it out.
The OP circuit is fine for triggering SCRs, where the series diode prevents reverse gate current, and blocks the G-K voltage during forward bias. Triggering should be the same way, a gated clock signal. The reaction (demagnetization) winding ensures clean operation at up to 50% duty cycle (though a clamp or snubber on the transistor drain might still be desirable).
Note that, due to the series diode, gate leakage will NOT be shunted by this circuit, and this may result in slower turn-off as well as greater sensitivity near rated voltage or temperature. (SCRs can be sped up somewhat by reverse-biasing the gate; indeed, GTO types can be turned off entirely this way.) I recommend a G-K pulldown resistor, say a hundred ohms or so, to provide this.
The question remains, why is the probed signal trash. The schematic seems fine, given that it lacks such a load resistor so the waveform will only be accurate during forward conduction. But the observation doesn't seem consistent even with that. The lumpy waveform and long timebase almost suggests a pinout error, and the probe is in fact not making a complete circuit through a secondary. Or the probe ground came loose (or the probe cable is frayed, as cheap ones tend to get), or etc.
Tim
-
Why is the waveform so nasty?
Tim
That's what I can't understand is why is it this noisy! even though I am connecting the cathode (K) to the GND of the PCB.
It is even much more nastier when I probe across the transformer output (GG & K only)!.
-
What thyristor are you using?
How much current can the logic circuit, or MCU output source/sink?
The pulse transformer can be configured 2:1 by connecting two of the secondary windings in parallel. This will result in double the current through the thyristor's gate, so the primary drive current can be halved.
Refer to the application note linked below.
https://www.st.com/resource/en/application_note/cd00003863-triac-control-by-pulse-transformer-stmicroelectronics.pdf (https://www.st.com/resource/en/application_note/cd00003863-triac-control-by-pulse-transformer-stmicroelectronics.pdf)
I am using S8006L thyristor.
This seems like a good idea, could you elaborate on how to do it based on the circuit I shared please?
-
When I have controlled SCR's I sent a burst of on pulses, closely together, to overcome any reluctance of the SCR to turn on, that way you are less likely to miss a cycle, they were however 1500V/2000A devices. I also would put a low value resistor across the output of the transformer/gate to try and prevent noise switching due to dv/dt.
Are you driving a thyristor gate, and is that the voltage waveform(yellow) across the gate? What is of more interest is the current pulse into the gate.
Yes, the yellow is the signal I get probing between the output to gate and cathode as shown in the circuit I posted (GG3 & K3), however this result was when I grounded the K as well, as without doing so the signal is very noisy.
-
Note that TRIACs have a back-to-back diode characteristic between G and MT1, so the above circuit is excellent for triggering them: the secondary resistance shunts gate leakage (improving stability at high temperature I suppose, maybe somewhat improving dV/dt immunity too?), while the diode characteristic ensures full conduction for both phases of drive. You use a gated clock signal to trigger it: the continuous up-and-down ensures operation in quadrants 1 and 2 (load positive) or 3 and 4 (load negative), and keeping the pulses going during operation ensures minimal dropout in case conduction angle isn't as expected.
The uh, gate still carries some voltage drop when on, doesn't it? SCRs for sure, TRIACs I don't actually recall. So you might want a series gate resistor on that still, so that the secondary DCR isn't shorting it out.
The OP circuit is fine for triggering SCRs, where the series diode prevents reverse gate current, and blocks the G-K voltage during forward bias. Triggering should be the same way, a gated clock signal. The reaction (demagnetization) winding ensures clean operation at up to 50% duty cycle (though a clamp or snubber on the transistor drain might still be desirable).
Note that, due to the series diode, gate leakage will NOT be shunted by this circuit, and this may result in slower turn-off as well as greater sensitivity near rated voltage or temperature. (SCRs can be sped up somewhat by reverse-biasing the gate; indeed, GTO types can be turned off entirely this way.) I recommend a G-K pulldown resistor, say a hundred ohms or so, to provide this.
The question remains, why is the probed signal trash. The schematic seems fine, given that it lacks such a load resistor so the waveform will only be accurate during forward conduction. But the observation doesn't seem consistent even with that. The lumpy waveform and long timebase almost suggests a pinout error, and the probe is in fact not making a complete circuit through a secondary. Or the probe ground came loose (or the probe cable is frayed, as cheap ones tend to get), or etc.
Tim
WOW Tim I really appreciate this great contribution, so much good info's included..
Actually as shown I am using gate resistance but it is 12.5ohm due to the fact I have 77202C transformer instead of the 77205C. Also this signal is without connecting any loads/SCRs to it, and I can't figure out the reason of this bad signal even though I had to GND the cathode of the output of the transformer to the PCB GND in order to make it this stable!.
I am going to use this PCB to drive thyristors from 1 thyristor (half wave controlled rectifier) to 6 thyristors (3-phase fully controlled rectifier).
It's not shown in the following schematic but I had to connect the neutral to the GND of the PCB to get pulses. And the The pulses shown in blue are getting from the 4081 gate to the 10ohm resistor gate of the 2N7000 transistor. Which makes me believe the problem is only in the part of the schematic I shared, but I am not quite sure.
I also use 8V (instead of 15V) and 5V to power the board as I was getting the 4081 fried before with the 15V power.
(https://i.stack.imgur.com/nSEg1.png)
-
What happens if you swap around probes?
Tim
-
What happens if you swap around probes?
Tim
this is the Gate to cathode output: https://www.veed.io/view/1cdc2a48-5604-40be-b3ed-2d535960a351?sharingWidget=true (https://www.veed.io/view/1cdc2a48-5604-40be-b3ed-2d535960a351?sharingWidget=true)
this is the cathode to gate output: https://www.veed.io/view/abfbf069-db63-48f2-9355-5900d3c76497?sharingWidget=true (https://www.veed.io/view/abfbf069-db63-48f2-9355-5900d3c76497?sharingWidget=true)
this is the Gate to cathode output when I connect the other probe ground to PCB ground: https://www.veed.io/view/bab8f925-7c04-4457-b1fa-98dc2c6c5df0?sharingWidget=true (https://www.veed.io/view/bab8f925-7c04-4457-b1fa-98dc2c6c5df0?sharingWidget=true)
-
How about something like this?
The anti-parallel diode will make the SCR's gate look more symmetrical to the pulse transformer.
(https://www.eevblog.com/forum/projects/would-this-signal-be-sufficient-to-control-thyristors-gate/?action=dlattach;attach=1457614;image)
-
No I mean, unplug the probes from the scope, swap them around, and plug in again, and swap what they're wired to...
That scope has TERRIBLE aliasing by the way. Just how crummy is it? And why not turn down the timebase to get a proper view of the pulse?
Tim
-
No I mean, unplug the probes from the scope, swap them around, and plug in again, and swap what they're wired to...
That scope has TERRIBLE aliasing by the way. Just how crummy is it? And why not turn down the timebase to get a proper view of the pulse?
Tim
The oscilloscope is a total fail unfortunately..
Here is the signals (with and without cathode to gnd of the PCB):
https://www.veed.io/view/276018c9-e57a-4569-af5d-f01b0216c2c1?sharingWidget=true (https://www.veed.io/view/276018c9-e57a-4569-af5d-f01b0216c2c1?sharingWidget=true)
https://www.veed.io/view/0468d260-e90d-47f2-b086-32eab01d3781?sharingWidget=true (https://www.veed.io/view/0468d260-e90d-47f2-b086-32eab01d3781?sharingWidget=true)
-
How about something like this?
The anti-parallel diode will make the SCR's gate look more symmetrical to the pulse transformer.
(https://www.eevblog.com/forum/projects/would-this-signal-be-sufficient-to-control-thyristors-gate/?action=dlattach;attach=1457614;image)
Unfortunately the PCB is already printed and assembled but I would try to give this a try..
-
How about something like this?
The anti-parallel diode will make the SCR's gate look more symmetrical to the pulse transformer.
(https://www.eevblog.com/forum/projects/would-this-signal-be-sufficient-to-control-thyristors-gate/?action=dlattach;attach=1457614;image)
Tried it, but unfortunately I didn't get any thing probing at the output diode D1... :-//
-
Please excuse my lack of experience..
I plugged an S8006L SCR to the triggering signal and I gotta say it became much more stable..
I probed between its Anode and Cathode, and here is the signal.. which I don't know if its right or not!
(https://i.ibb.co/fSf29Dc/unnamed.jpg)
-
It looks good to me,
-
It looks good to me,
You just drew a smile on my face, literally ..
Can you please explain the signal to me ?
-
I forgot to say, that if your input signal is a burst of 5 pulses, then it's correct, otherwise I don't know where the 5 pulses are coming from.
The internal diode structure of SCR clips the voltage at about 0.7V and the transformer's inductance allows the current to flow for a short period of time between pulses,
-
I forgot to say, that if your input signal is a burst of 5 pulses, then it's correct, otherwise I don't know where the 5 pulses are coming from.
The internal diode structure of SCR clips the voltage at about 0.7V and the transformer's inductance allows the current to flow for a short period of time between pulses,
Yes I am using train of pulses.
THANK YOU SO MUCH.. I am really thankful for your help Zero..
-
Sorry to dampen your good results, but the voltage should reach zero between the pulses so that the magnetic core is fully reset, otherwise you can saturate it, though it doesn't appear that you are. If you can extend the period between the pulses so that they reach zero after each pulse that would be good. Just my opinion though.
-
Sorry to dampen your good results, but the voltage should reach zero between the pulses so that the magnetic core is fully reset, otherwise you can saturate it, though it doesn't appear that you are. If you can extend the period between the pulses so that they reach zero after each pulse that would be good. Just my opinion though.
Hello moffy thank you for your good point, so the only way is to keep trying with the off cycle until I get it to reset to zero..
-
Yes, a clean return to 0v and staying there, like at the end of the pulses indicates that the core has reset its magnetic flux. There are some simple equations:
V = L*di/dt = N*dPhi/dt where Phi is the magnetic flux.
So when V=0, the dPhi/dt is zero and the flux in the core has reset. These simple equations are valuable to remember. :)
-
I have changed the power supply voltage to down to 5v for all board. Turn out powering the ic's with 8v while Arduino generate 5v pulses caused me issues in the AND gate output..
What do you guys think of these sginals:
Signal with pulse trains OFF, yellow is the transformer output and blue is the Anode-Cathode signal.. (Idk what these two spikes after the pulse are).
[attach=1]
Signal with pulse trains , yellow is the transformer output and blue is the Anode-Cathode signal..
[attach=2]
-
I don't know what's going on in the first image, but the second one looks fine.
By the way, please use the save pic option to generated a .png file, rather than posting big arse pictures.
-
If I remember correctly your pulse transformers have a maximum Vus = 120 Vus. At 5v on the primary that gives you a maximum on time of 24us (5*24=120), lets say 20us just to be safe. So on pulses with an ON period between 10us to 20us should be fine. But whatever ON period you choose you should make it consistent, each ON the same, and you should allow the pulse transformer to reset to zero between each pulse as previously mentioned.
-
Seems like the TCA785 needs no less than 8v supply to operate.. I guess I have to add a small MOSFET circuit to the Arduino output in order to increase its pulses voltage output to the 4081 gate.....
-
The latest update for this long sad story..
After I had pulses out of the pulse transformers, which were with different voltages that made me think they all will be ok to trigger my SCRs..
When I applied them one by one to the S8006L in real life I got some that are able to fire it and some couldn't!!!!
I was wondering if that the pulses are getting to the gate of the 2N7000, and it switches the primary windings. And the pulse transformers are fine. Then what could make some of the pulse transformers output to be lower than what it supposed to be?, is there anything other than a bad 2N7000?.
-
Did you 'scope the gate?
A bad 2N7000 is the obvious place to start. Have you tested it?
-
Did you 'scope the gate?
A bad 2N7000 is the obvious place to start. Have you tested it?
Yes Zero it was a bad 2N7000, which was testing ok on the multimeter with minor deviations.
But I should get rid of all the low quality FETs now..
-
Did you 'scope the gate?
A bad 2N7000 is the obvious place to start. Have you tested it?
Yes Zero it was a bad 2N7000, which was testing ok on the multimeter with minor deviations.
But I should get rid of all the low quality FETs now..
How are you storing them? MOSFETs, especially smaller ones such as the 2N7000, are very sensitive to electro static discharge (ESD).
-
Did you 'scope the gate?
A bad 2N7000 is the obvious place to start. Have you tested it?
Yes Zero it was a bad 2N7000, which was testing ok on the multimeter with minor deviations.
But I should get rid of all the low quality FETs now..
How are you storing them? MOSFETs, especially smaller ones such as the 2N7000, are very sensitive to electro static discharge (ESD).
Yes most probably it was that!
Now I am annoyed that I am not able to control the Alpha angle as I hoped to. I almost couldn't move it at all with the 10Kohm pot that is suggested in the datasheet, I am now using 1M ohm pot and I have more control over it's angle, but still not as great as I see people do..
(I am using single turn pots).