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XMOS breakouts

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snx:
Hi,

This question is about xmos beakouts. They are basically an XMOS Audio "I2S-USB" chip solderd to pcb including oscillator.

Here are a few examples:

https://www.diyinhk.com/shop/eol-product/58-xmos-dsd-dxd-384khz-high-quality-usb-to-i2s-pcb.html#/xmos-xmos_384k_pcb
https://hifiduino.wordpress.com/2013/04/16/got-the-xmos-384khz-usb-interface/

I'm not 100% sure how these chips work, how do they know what type of DAC IC you connect? I would like to use this breakout for a INPUT, so i would have to connect a 384 kHz ADC instead of a DAC. I don't know alot about I2S, but is it possible that the xmos ic does automatically discover what type of device is on the I2S line?

Would this board work with ADC?

mikeselectricstuff:
I2S is pretty simple & standard so the Xmos chip probably doesn't need to know.

SiliconWizard:
On those boards, the XMOS chip acts as an I2S master controller. It has no knowledge of what you connect it to. It will output MCLK/BCLK/LRCK (that you'll need to connect to your ADC), as well as output one or several I2S data lines  (for DACs), and input one or several I2S data lines (for ADCs). Your ADC will have to be set up as an I2S slave. As long as it supports the sample rate that the XMOS will use, there's no need to know anything more about it. I2S is standard, and in most cases, audio data is received/sent as two 32-bit words regardless of the sample width, in an MSB-first way (the remaining bits being usually zero), so basically, BCLK (bit clock) will be the sample rate times 64 (two channels, L/R, per I2S frame).

bson:
The XMOS chips I've looked at don't directly support I2S, but what they do have is externally clocked GPIO shift registers with FIFOs.  This is a key feature, as the clock isn't derived from the CPU clock but is bus specific.  More specifically, you'd find it VERY difficult to use the same timebase for both USB (48MHz) and 44.1k audio.  So what you do is load up a FIFO using DMA and it ends clocked out on a pin.  The chip has no knowledge of the various I2S formats.  Since you need to interleave L/R and generate additional signals what I would do is dedicate a core to managing each interface.  (These chips have a bunch - very primitive peripherals plus lots of lightweight cores, a pretty good design but requires solid system design skills.)

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