Electronics > Projects, Designs, and Technical Stuff
yet another GPSDO
1001:
I am planning to build a James Miller style GPSDO using an ISOTEMP OCXO 134-10 ocxo and a NEO-M8T gps module. I'm not sure what is the best compromise of the frequency for the phase detector (a XOR gate), this could be between 8khz (or lower) and 1 Mhz, in the attached schematic is 62,5khz, any suggestions? U1 is a PICDIV programmed to divide by 80 (thanks to TVB, www.leapsecond.com/pic/picdiv.htm).
Gyro:
I did some playing around at 1MHz and 100kHz... https://www.eevblog.com/forum/projects/my-u-blox-lea-6t-based-gpsdo-(very-scruffy-initial-breadboard-stage)/
David Hess:
I would use an LT1008/LT1012/LT1097 instead of the LT1006 for lower input bias current so the value of the expensive input capacitor can be lowered although this may require a negative supply. The feedback resistor should be bypassed for lower noise. U6 should be powered by a precision supply.
There are some tricky analog ways to cancel the leakage in C8 but I do not think they are necessary when C8 is inside of a feedback loop as it is here.
1001:
--- Quote from: Gyro on January 10, 2019, 10:27:53 pm ---I did some playing around at 1MHz and 100kHz... https://www.eevblog.com/forum/projects/my-u-blox-lea-6t-based-gpsdo-(very-scruffy-initial-breadboard-stage)/
--- End quote ---
so 100KHz seem to be the best compromise for you, I think so too and I could increase it to 125Khz to get 250Khz at the out of xor gate with the advantage of less ripple at the vco in as long as filter capacitor allows it. Naturally I will have to change the firmware of U1 to divide by 40.
iMo:
I've been using 10kHz (or 20kHz recently). Not sure large value capacitors work well at higher freqs (I need something like 50-100uF caps in the loop filter). Also I use an higher order filter with buffers - see the schematics:
https://www.eevblog.com/forum/projects/help-to-designselect-a-pll-to-clean-up-a-gps-signal-for-a-reference-standard/msg1717559/#msg1717559
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