I think you can solve it with a single 74HCT157 - Quad 2-input multiplexer. See attached schematic.
I didn't redesign the parts already in your schematic. "Dn_Latch" are the outputs from the 74hct273 (with an extra D2), "1Y" is the same as yours (area 2 selected).
If other area is selected A16=0, SRAM_A14/A15=CPU_A14/A15
If area 2 is selected, A16=D0, A14=D1, A15=D2 (change as it best suits you, it was made in a rush).
This way you can map any memory area to area 2, so be careful :)
I think you can solve it with a single 74HCT157 - Quad 2-input multiplexer. See attached schematic.
I didn't redesign the parts already in your schematic. "Dn_Latch" are the outputs from the 74hct273 (with an extra D2), "1Y" is the same as yours (area 2 selected).
If other area is selected A16=0, SRAM_A14/A15=CPU_A14/A15
If area 2 is selected, A16=D0, A14=D1, A15=D2 (change as it best suits you, it was made in a rush).
This way you can map any memory area to area 2, so be careful :)
Need to get your head around memory management. It can be simple, your computer is doing it now....
[SNIP]
This is greater then what you asked for, but in the process uses few general chips and works with power on.
Would an SN74HCT257N be a suitable replacement for the 74HCT157? I'm trying to avoid SMD if at all possible as my soldering skills are probably not up to it!
What I need to be able to do, having looked at the CP/M 3 System Guide, is to make areas 0, 1 and 2 switchable. This adds a layer of complexity that is far beyond my simple electronics knowledge and understanding, unfortunately.Using a 74140 or 74LS670 allows you to map any memory segment (e.g. 16k) to any e.g. 16k as seen by the Z80.
Look at your last design.
You have more bits in the 273 & one more 1 of 2 switches.
This one bit lets you have A17.
When A17 = 0 rom is selected.
When A17 = 1 ram is selected.
You can get this to happen just by proper connection to rom & ram chips.
You now have 8 banks you can swap in to area 2, 4 ram & 4 rom.
This change is a step to removing all the other chips used to swap rom for ram.
Your switch is a 2 throw switch & is selecting normal Z80 or Banked, but banked is only used for area 2 which needs extra logic to select.
You can remove the logic that selects area 2 by using a 4 throw switch!
Two 153 would let you do this. A 153 is a dual 1 of four switch.
By connecting Z80 A14 & A15 to the 153's A & B inputs, the switch it's self will decode the area removing need for area2 select. For now just strap other inputs to proper levels for the fixed addresses like you have with the 257.
Now if you look at 273 you have 4 bits not used. If you used these 4 bits to select the bank for area 0 you could remove all the other logic that selects rom/ram for system.
Area 0 would point to 0-16k on power up and by writing the 4 bits can point to any block of ram or rom.
This leaves 8 inputs to the 153 strapped to a level. By adding one 273 you have bits needed to change these pins and all areas can be banked as needed.
So two 273's and two 153's give you four areas that are bank selectable & you get to remove current logic that selects rom or ram swap.
You should note that CS for the rom & ram chips selects chip active or disabled/sleep.
If A17 & Z80 MREQ is used for Chip select then Z80 RD & WR can be directly connected to these chips.
Need to look at big picture when thinking about a change.
You locked into changing only area 2 and not looking at total system and a change that would get a better result.
Worth looking at the design of the ZX Spectrum 128, which banks memory in the top page of the Z80's address range. It's quite a simple mechanism.
Looking at the SIO the CE pin would go low(active) when proper address is valid and stable and IORQ is active. U5 is missing a IORQ input to enable pins to make this case.
I didn't read all the post in this thread in detail, so maybe I'm stating something already discussed, sorry.
The system I worked on was S100 buss based and the memory cards were 48K each and had a dip switch that set the IO port number that the card would listen to to turn it on or off. It was up to MP/M to keep track and only have one card enabled at a time. One card in the system had a full 64K, and the lower 48 could be disabled again with an OUT command.
Maybe look for old schematics of those S100 boards and see what they did. At least you know CP/M 3.0 will work with with that method of memory management.
By writing to the latches you can map any bank of RAM or ROM at any 16K page in the address space. However you would do well to rearrange the input lines to the multiplexors so EA14-EA17 for a single page are controlled by four bits on the same latch, otherwise it will be difficult to switch mappings without smashing the mapping for the page that is currently executing.
However this seems over-complex. Personally, I'd use a 74HC670 4x4 addressable register file to expand the addressing. It does *NEARLY* everything the above circuit does in one chip. That would give you a separate port write to control each page, with two bits in the data selecting the page and four bits selecting the bank, but would need the addition of a flipflop driving its /RE pin (that controls its output tristate capability) set by /Reset and cleared by an unused data bit decoded at the port address+ 10K pullup or pulldown resistors to set the default powerup mapping.
You are getting there keep up good work.
Now look at the 74LS670.
It is a 4 X 4 memory chip.
It has a data & address port for writing data.
it has a data & address port for reading data.
It has NO reset input.
It has a tri-state output for read data port.
This chip does all most the same thing as the two 273's & two 153's
To get valid data on output pins at power up,
You connect pull-up resistors to the Read data port that is connected to memory, when you enable tri-state mode the resistors will supply a 1 to memory address line.
If you changed the MMU to use 4 sets of 8 bits then the total memory would increase to 4m.
This would be two sets of 4 chips or 2 74LS670's
Keep in mind what you might want to do in the future.
The 512k dip memory I found was in a 32 pin package.
The Z80 being able to access a lot of memory space is a powerful thing.
Memory does not have to be memory.
Some CPU's have I/O in memory space.
The extra memory space could be connected to other processors.
B7 B6 B5 B4 B3 B2 B1 B0
Boot -- S15 S14 EA17 EA16 EA15 EA14
LD B, high(PORT) ; assuming full IO address decoding
LD C, low(PORT)
LD A, $80 ; High bit set to stay in BOOT mode
OUT (C),A ; set page 0 to bank 0 - the first 16K block of ROM.
LD A, $99
OUT (C),A ; set page 1 to bank 9 - the second 16K block of RAM
LD A, $AA
OUT (C),A ; set page 2 to bank 10 - the third 16K block of RAM
LD A, $3B ; High bit clear to leave BOOT mode
OUT (C),A ; set page 3 to bank 11 - the fourth 16K block of RAM
Once execution is transferred to RAM, you can remap page 0 to RAM as well. Because you want to keep the '690 enabled keep bit 7 clear: LD B, high(PORT) ; assuming full IO address decoding
LD C, low(PORT)
LD A, $08
OUT (C),A ; set page 0 to bank 8 - the first 16K block of RAM
Erm.. where? Are you talking about D1-D3 on the schematic?on 74LS670 pin GR(11) controls the tri-state of Qn outputs.
I cant conceive of needing more than 1MB address space for a Z80 system
In the topic I linked to in the O.P.s earlier Z80 thread (https://www.eevblog.com/forum/beginners/z80-bank-switching-using-iorq/), I contributed the concept of using a '486 era fast cache SRAM to do the mapping. The spec was to map 1MB into the Z80 64KB in 4KB blocks. Propagation delay was solely dependent on the SRAM used, possibly as low as 10ns.
Drive '670 /WE and flipflop CLK in parallel from your port address decode logic which should include Z80 /WR.
nockieboy
Grab a some paper and then work through this post
https://www.eevblog.com/forum/projects/z80-memory-banking-for-128k-mmu-design/msg1345498/#msg1345498 (https://www.eevblog.com/forum/projects/z80-memory-banking-for-128k-mmu-design/msg1345498/#msg1345498)
The drawing you create should be a big help in understanding both the 4 chip MMU and the 74ls670 version.
Think it will help a lot.
To get the 74LS670 to work
You need one output from the 273 connected so that a 0 makes the 74LS670 output goes tri-state.
OR
You keep using grant's logic and have ROMDisabled connected to 74LS670 tri-state input pin 11.
1) Where do those pull-up/downs go to select ROM bank 0 (lowest 16K in ROM) for Area 0 (lowest 16K in memory space) and RAM bank 1 (16-32K in RAM) for Area 1 (16-32K in memory space) on power-up?? (That's the minimum requirement to get the monitor running - once running, it can set up the memory as it likes.)
No. the ROM has /CE and the RAM has CE2. Pulling up EA17 (aka Q4, RAM/ROM_SELECT) would select the RAM at booot - pretty pointless.
However the RAM and ROM *PROBABLY* have CMOS input thresholds. If so, a pulldown is legitimate. If they have TTL thresholds, (or worse there is an actual bipolar TTL gate input on that line), then stick a pullup on Q4 and follow it with a CMOS inverter to drive the ROM /CE and RAM CE2. That would also swap the positions of the ROM and RAM in the memory map.
If you go with my suggestion for decoders, you get at the top level 16 address blocks, so no problem hooking up a CF card with three address lines. However a CF card has TWO chip select lines, that select different register sets so you still need to combine A3 with the 16 address block /CS from the top level '138.
Gr is High for tri-state so at power up reset the FF output connected should a 1 HIGH
Here you have a lot of options using the 74
Would be nice when you write to this port for D7 to be low normally so when clocked by I/O write you will get a state on the two outputs. Here you want a low level on
D7 low on I/O write which makes Gr = 0 The Q output.
At power UP you then write the first 4 times with D7 high.
Then turn on MMU by a write with D7 low
So with this being what you want for normal, you have a choice of preseting this chip on power up or clearing this chip on power up.
So if I am thinking correct Power Up preset Sets the FF to cause Q= 1 -> Gr which tri-states 74LS670 outputs.
So if your RESET goes Low at power up and is connected to preset you are good.
In place of 74
Now If you are going to have a 273 that is reset at power up you could use a bit there in place of 74 FF. BUT the 273 only resets to 0 so you would need and inverter between 273 bit and Gr.
And to be complete you could use grant's existing logic to do this. Not my choice unless you want to use it while making the change.
Would suggest you put this on separate breadboard or on memory breadboard.
You could leave the Q1-Q4 disconnected from memory and do some tests to verify you have built this correctly.
Decoder
remember that you do not have to use all outputs.
If you have nothing connected then nothing will respond to that address.
You could build a new decoder and slowly move outputs from U5 to new.
In the future, think you would like a decoder for
One address I/O Write (273,374 & lan.M MMU )
One address I/O Read
Four address I/O for (SIO, CTC PIO)
Then I think the CF card is using 8 addresses. Would need to look in the software to verify it is using 8 and not less.
You could OR two 4 address outputs, but Need to test to see if it works with added delay of OR gate.
Need to keep track of what is connected and how much load each thing adds to Z80 output. Z80 has limited output.
However the RAM and ROM *PROBABLY* have CMOS input thresholds. If so, a pulldown is legitimate. If they have TTL thresholds, (or worse there is an actual bipolar TTL gate input on that line), then stick a pullup on Q4 and follow it with a CMOS inverter to drive the ROM /CE and RAM CE2. That would also swap the positions of the ROM and RAM in the memory map.
A cheap and easy way of adding more FLASH ROM would be to connect the remaining unused data bit at the MMU port address to the other half of the boot mode flipflop chip, in exactly the same way. Then instead of the inverter between EA17 and the /CS line to the ROM, take the Q and /Q from the new flipflop, each to one input of a pair of NAND gates, with their other inputs from EA17. That gives you two ROM /CS signals, each suitable for a 128K chip without increasing your glue logic chip count. At boot, the flipflop would be set, so the NAND fed with Q would generate the active /CS.
How you doing understanding a MMU?
Now some things you might not have noticed.
There is JEDEC Standard for a – 32-pin PDIP
Part of standard covers the pins, part software for non tam/rom , parts like flash eeprom.
The datasheet for your flash rom table 4 shows this for a 32 pin socket. If you were planning a PC board, with some care, it could be used with many sizes of chips.
Note the software steps for your Flash Rom to write data again part of JEDEC
So table 4 gives you a list of pins to check how the use of pins change with size
pin 30, pin 1 , pin
I would wire up pin 31 to both chips so in the future you can write to flash using Z80.
You are using a inverter here. If you had more 128k chips, you should use a decoder like 138.
Older memory chips do not support the way these chips are used and you would have MREQ connected to decoder enable instead of where MREQ is connected now.
You have been working with Grat's software for a while now.
Have you seen Grant's code use any thing other than
OUT to address 0H with some data value?
LD A,01
OUT (38h),A
A list\
IORQ & RD = i/o read input
IORQ & WR = I/O write output
IORQ & M1 = Interrupt ack
The second item is unique
The Z80 never makes WR & RD active at same time.
Remove M1
M1 will not hurt any thing just that If needed it is a sign of some poor interface.[/b]
AY sound could need M1 so leave it connected
Suggest that you connect a new 138
A0 -> A pin 1
A1 -> B pin 2
A2 -> C pin 3
Wr -> E3 pin 5
pull-up E1 pin 6
current 138 Y7 pin 7 38-3F to new 138 E2 pin 4
Grants that was connected to current 138 Y7 move to new 138 Y0 pin 15
You have 7 outputs that will work for MMU pick one.
The reason I've done it this way and not your suggested way is because I didn't want the MMU's select line sitting behind another 138 (with the associated additional propagation delay that would introduce) and it would still be sitting behind the ~M1 line which would still be attached to U5.
The internal control logic synchronizes the CPUNote the PIO has no WR pin
data bus to the peripheral device interfaces
Keep in mind that the Z80 does not have to run at an even MHZ. A Z80 can be faster with a little slower clock if memory changes from 1 wait state to 0 wait state.
A wait state is a step in time.
Okay, so that leads me on to a (vaguely) related question - is there such a thing as a programmable oscillator or frequency divider? The reason I ask is that I can ch7ange the frequency of my SBC in software between 2, 4 or 8MHz, but I need a fixed 2MHz signal for the PSG, so whenever I change the system clock frequency, I'd like to be able to maintain a 2MHz frequency for the PSG. I'm guessing a separate, dedicated 2MHz oscillator is probably the simplest and cheapest option...
EDIT: ... except a separate oscillator will mean the PSG is running out of sync with the SBC's system clock, which could cause timing problems of its own. I've just done a quick search for 'programmable oscillator' - the cheapest I could find was like £50 (~$70?) Ouch!
Ah, 74LS294 - programmable frequency divider?
As you identified, the clocks need to be synchronous unless special precautions are taken.
A synchronous counter can produce all of the needed clocks simultaneously and then a multiplexer can select which one is used. Special precautions may be necessary to prevent glitches and clock violations.
So - would something like a 74LS163A (http://www.ti.com/general/docs/lit/getliterature.tsp?genericPartNumber=sn74s163&fileType=pdf) be suitable? I'm guessing I'd only need a 4-bit counter, rather than a decade counter, as I only have to get 2MHz from an 8, 4 or 2MHz system clock speed? Unless I completely misunderstand the principle, a 4-bit counter would give me 4, 2, 1MHz and 500KHz from an 8MHz input clock, halving down accordingly with lower (4 or 2MHz) system clock speeds?
From what I am reading, guess you did not do slow changes with verify steps to see each part is working.
Note that with all ROM the Z80 STACK is not working.
The Z80 boot software should be able to start and send a message to serial even with out STACK working.
;------------------------------------------------------------------------------
; START OF MONITOR ROM
;------------------------------------------------------------------------------
MON .ORG $0000 ; MONITOR ROM RESET VECTOR
;------------------------------------------------------------------------------
; Reset
;------------------------------------------------------------------------------
RST00 DI ; Disable INTerrupts
JP MINIT ; Initialize Hardware and go
MINIT:
; Initialise MMU
LD C,MMU_IO ; Set C to IO port of MMU
LD A,$8F ; MMU disabled, Page 0 = Bank 0F
OUT (C),A
LD A,$91 ; MMU disabled, Page 1 = Bank 01
OUT (C),A
LD A,$A2 ; MMU disabled, Page 2 = Bank 02
OUT (C),A
LD A,$33 ; MMU enabled, Page 3 = Bank 03
OUT (C),A
LD A,$3 ; Set MMU_Lock byte so that Areas 0 and 1 are locked
LD (MMU_Lock),A ; from inadvertant re-mapping by the BANK command
LD SP,MSTACK ; Set the Stack Pointer
LD HL,serABuf ; Set up Serial A buffer
LD (serAInPtr),HL ; with In and Read pointers
LD (serARdPtr),HL
LD HL,serBBuf ; Ditto for Serial B
LD (serBInPtr),HL
LD (serBRdPtr),HL
XOR A ; 0 to accumulator
LD (serABufUsed),A ; Set both buffer sizes to zero
LD (serBBufUsed),A
Now if the MAD Software creator happened to write some code.
The code could write some values to the 670 and let you test the 670
Even with out the STACK working a JP will work.
At boot Z80 A14 & A15 = 0
If boot code jumps to the different areas what is on A14 & A15 will change
So code is running in area 0
do a jump where A14 & A15 change to area 1 with the lower bits set for instruction after the jump
With the boot code showing in all four areas, the Z80 could jump between the areas and stay in that area a while by doing a loop.
While looping you could output a message to serial.
The Z80 could try to write to memory & read memory.
Note that the ROM write has a software safety lock so even with ROM's WR pin connected, Rom should be un-changed.
Crap meter should read close to same value for same voltage.
If you measure USB Voltage with crap meter then you should get very close to same value every where for 5v.
With the memory mode you are running the memory in, you need U8:A & U8:B wired like grant's drawing. Pins 3 & 6 connect to ram/rom grant's way.
Pin 3 to ram WR
pin 6 to RAM & ROM OE
All Ram/rom address/data lines go to Z80
Except for A14 and higher.
Did you get the High 16k area of ROM programmed properly?
It should match first 16K except for those bytes in the message.
EDIT ADD
The MMU control is output only.
You will need MMU area values when you try to get back from using or working with a different area.
Software FIX
You have a copy of what was last written to MMU in common memory.
When you start to make a change to a new bank,
1. push a copy of common memory MMU values on to stack
2. as you make changes to MMU change common memory MMU values also.
Use the new MMU map
3. on return from using MMU map
Read old MMU values from stack and update MMU and common memory MMU values
This setup lets you change MMU many times and return back to previous settings.
This is foundation for what could look like magic.
OK
bank
Current memory mapping:
AREA 00 -> BANK 00 (RAM) *LOCKED
AREA 01 -> BANK 01 (RAM) *LOCKED
AREA 02 -> BANK 02 (RAM)
AREA 03 -> BANK 03 (RAM)
RAM: 64KB, ROM: 00KB
OK
bank 02,06
OK
bank 03,0b
OK
bank
Current memory mapping:
AREA 00 -> BANK 00 (RAM) *LOCKED
AREA 01 -> BANK 01 (RAM) *LOCKED
AREA 02 -> BANK 06 (RAM)
AREA 03 -> BANK 0B (ROM)
RAM: 48KB, ROM: 16KB
OK
bank 00,0f
Cannot remap locked Areas
OK
Also see https://www.z88dk.org/ (https://www.z88dk.org/) for a relatively modern toolchain for Z80 cross-development in assembler and C.
Think you are ready to work on CP/M3
For long term
Think it would best to use CP/M3's relocating assembler.
Some programs/code contained their own reallocators in memory.
The ones I remember used a simple bit table to change the value of a byte.
You assemble code two times with a ORG change of 100H
The binary bytes that are different are the bytes needing to change to move code in steps of 256 bytes.
From memory SID and ZSID did this.
Now that you have a MMU, what other areas do you want to learn?
I am assuming that you now know what would need to be changed if you wanted to use larger memory chips or a larger address space.
I'd have to look at the details, but I believe that would permit a CP/M Plus or MPM system to have nearly 60K of TPA!You do not need a 4k page size to get 60k of TPA. My CP/M3 system I built in the early eighties used 32k page size with 62k TPA.
But thinking ahead, I'll need to upgrade my current MMU to allow for another two address lines (EA18 & EA19.) This can easily be done with the addition of another 74LS670 chip, but what would be the best way to wire it in to the existing MMU circuit? I presume EA17, the existing ~RAM/ROM select line, would become the ~GR input for the second 670 and I'd remove the inverter to place it on EA19 coming out of the second 670 and going to ROM?
A minimum of two and up to sixteen banks of memory with the top
4K-32K in common memory. Bank 1 must have contiguous memory
from address 0000H to the base of common memory.
If your MMU permits fast paging in 4K blocks, (giving an address space of 1MB), a 16 x 60KB CP/M bank system is possible using a total of 964KB of RAM. That's two 512KB (4Mbit) RAM chips, leaving 60K unused.
If you hook up the /WR signal, you can also write to the FLASH, but I'd make that manually switchable to avoid rogue code smashing your bootstrap or system disk. With an appropriate utility (to run from RAM), that would allow re-flashing your system in-situ.
Is it too late to chuck this (http://mdfs.net/Info/Comp/Z80/Circuits/1MbMem.gif) in the mix?
(I only stumbled across this forum yesterday)
Why not do the easy thing?
You have CP/M running.
There are many programs that allowed one CP/M computer to talk to another computer and transfer files
file transfer protocols
Kermit
XMODEM,YMODEM, ZMODEM
Some of these are built in to a PC terminal program
TeraTerm is one of many for PC side
It should be easy enough to understand. Think about it some more and consider what it would take to feed the Z80 a known sequence of opcodes and data bytes in place of what would normally come from the external memories. If you want to use a smaller ATmega, it needs a couple of shift registers so it can do the Z80 data bus interface via SPI, to save pins, it doesn't hook up to the address bus but does need several control signals and some of them have to be intercepted - do that with analog switches to minimise the propagation delay when the hardware bootstrap/debugger is not in control - and some glue logic to handle some control signals that are too fast for the Atmega to handle in code.
My explanation of how you can make the ATmega bootstrap the Z80 is really not that tricky, and doesn't need a deep knowledge of the bus timings - or at least no more so than you need to build a Z80 system that's more complex than a minimal one in the first place. The idea of a zero CPU resources hardware debugger is however a lot more complex so I quite understand your reluctance to start down that road at thios stage. Its something you could retrofit later by adding a daughterboard carrying the hardware bootstrap/debugger between the Z80 and its socket. Adding mounting holes to permit such a daughterboard to be secured with PCB standoffs would future-proof your design.
However if you aten't going to have a hardware bootstrap of any sort, then you are up s--t creek if the boot block in the FLASH chip gets corrupted.
If you want to avoid having to pull the FLASH chip to put in your programmer, I strongly recommend writing a monitor ROM that can cold-boot the machine, and can also receive data in IntelHEX format and store it to RAM. Burn it to EPROM and provide a socket for it on your memory board. You'll also need a SPDT switch to select between routing the ROM chip select to the FLASH or the EPROM, while the non-selected one is held inactive by a pullup on its /CS pin.
Then if you brick the FLASH bootblock, you can switch to the monitor ROM, restart anduse it to load an IntelHEX downloader + FLASH writer utility into RAM and run it, then flip the switch back to select the FLASH before sending it the FLASH image to be programmed.
You are working on CP/M BIOS. One small function is write sector or block. You will be reading/writing blocks of ram. Small change to have a Ram disk. An it's a second small change to have a ROM disk.
You can have CP/M use part of chip and have your bios capable of writing any area of chip.
When you can read/write blocks of a rom/ram you can then use CP/M format command to create a working disk.
With good foundation steps it becomes easer to expand.
You should know answers to my above questions if you go step by step changing circuit as lan.M suggests.
You cant wire the switch as you have drawn as the LED will prevent the level going low enough for a valid logic 0. Move the logic takeoff point to the LED cathode and a 4K7 resistor across the LED to fix it.
How about using the HD64180 ?. it already has an MMU giving access to 512K of memory plus other facilities. It was marketed as a "Super Z80" and sold by Zilog as the Z180. You can still find them : https://www.ebay.com/itm/Hitachi-64180-Kits-HD64180-MPU-TC551001-128K-SRAM-W27C020-EEPROM-DIP32-/161337103516 (https://www.ebay.com/itm/Hitachi-64180-Kits-HD64180-MPU-TC551001-128K-SRAM-W27C020-EEPROM-DIP32-/161337103516)
An example of its use is at https://www-users.cs.york.ac.uk/~pcc/Circuits/64180/doc.html (https://www-users.cs.york.ac.uk/~pcc/Circuits/64180/doc.html)
Ken
You have all the answers you need to answer your question from Ian.M's post.
Now go a step further and change how switch is connected.
Wire the switch with C1 connected to ground.
If you understand Ian.M's post, this is a small change.
Now what happens when connection to U4 pin B gets disconnected or switch fails?
Do not make it hard, take simple steps from first drawing to improversion of last drawing.
Start here in postYou should know answers to my above questions if you go step by step changing circuit as lan.M suggests.
You cant wire the switch as you have drawn as the LED will prevent the level going low enough for a valid logic 0. Move the logic takeoff point to the LED cathode and a 4K7 resistor across the LED to fix it.
Understanding now will save you time later.
Now continue reading lan.M's post.
It's probably entirely wrong but, if it's not, how does the LED not light up when the switch is open? Surely it's earthed via U4:B? And what is the purpose of the 4K7 resistor in parallel with the LED?
Surely it's earthed via U4:B? And what is the purpose of the 4K7 resistor in parallel with the LED?
Thanks Ken - but the reason I haven't gone for a more modern processor / microcontroller is because it defeats the purpose of doing all this in the first place - to build something similar in capability to my first ever computer, and maybe learn something about electronics at the same time.Then why all this talking about flash memory and extreme amounts of memory? Imagine that the memory cost is about 5 UKP per kilobyte static RAM and build with what you "can afford".
Thanks Ken - but the reason I haven't gone for a more modern processor / microcontroller is because it defeats the purpose of doing all this in the first place - to build something similar in capability to my first ever computer, and maybe learn something about electronics at the same time.Then why all this talking about flash memory and extreme amounts of memory? Imagine that the memory cost is about 5 UKP per kilobyte static RAM and build with what you "can afford".
Your last will work!
Your flash rom has a software protect feature to prevent accidental writes.
You should be able to just connect your existing /WR that goes to RAM to your Rom chip with no problems.
With some good code even CP/M2 can use a RAM or ROM drive.
With CP/M3 capability to run a program on CP/M2 and change to CP/M3 you have a great test environment.
Build a NON-Banked version of CP/M3
Use this to build two more CP/M3 versions
CP/M3 with ROM and/or RAM disk drives.
Banked CP/M3
Banked CP/M3 with ROM and/or RAM disk drives.
For future keep in mind that a CP/M disk drive could be a file or array of blocks on PC or something.
What is the best/easiest way to have the 74AHC74's output seem like an open collector to the Z80? Use a schottky diode?