Hi everyone,
Okay, I've been busy learning more assembly and writing CP/M software for my Z80 SBC these past few weeks and now I'm taking a break to finish off a couple of hardware tasks I'd like to complete on it.
I'm having more than just a little trouble getting my head around designing an MMU for my Z80 that will allow it to use a 17-bit (128KB) address space.
For those that are unaware of my lengthy previous post in these forums regarding Z80 fault finding, I'll just state that my software capability far outstrips my hardware and soldering skills. My Z80 currently resides on a breadboard, but is otherwise a fully-functioning computer with 64K SRAM, CTC, SIO/2, PIO and an Atmega328 micro-controller providing multiple speeds of system clock (2, 4 and 8 MHz selectable from CP/M 2.2 which runs just fine from the CompactFlash card.)
It has a 128KB SRAM chip, though and I would really like to be able to give the Z80 access to the full 128KB of SRAM goodness. However, after much digging online and finding precious little regarding MMU designs for the Z80, I am resorting to asking here for a bit of a leg-up on the circuit design.
Here's the design specs (or intended memory map, if you will):
![](https://preview.ibb.co/dBOfYG/Untitled.png)
So as you can see, I want to divide the memory space into 4 blocks of 16KB:
Area 0, the base 16KB of memory, will be fixed as this forms the ROM space when the computer first boots up and, when CP/M is running, this area is RAM and houses a lot of important CP/M vectors and the start of the TPA.
Area 1 is the second 16KB of RAM space and, if CP/M isn't running, houses a lot of important information for the ROM like the stack, command buffer etc.
Area 2 is the top 16KB of the TPA in CP/M and free memory - so this is the 16KB bank of RAM I'd like to be able to switch with one of the four 16KB banks in the upper 64KB of the SRAM.
Area 3 is the top 16KB of the 64KB addressable by the Z80 (the bottom half of the 128KB SRAM) and is where CP/M, CBIOS etc reside.
So I'd like to be able to swap in any of four 16KB banks in the upper half of the 128KB SRAM into Areas 0, 1 or 2.
So what have I tried so far? ![Confused :-//](https://www.eevblog.com/forum/Smileys/default/confused0024.gif)
Well, aside from hunting out some not very helpful schematics online, like this one
https://sites.google.com/site/oldcpusrus/home/simple-mmu-for-the-z80, which confuses rather than helps me (remember I'm not so hot on the electronics side), I came up with the beginnings of an MMU design on the back of a fag packet (or would have been if I smoked):
![](https://preview.ibb.co/ebug7b/20171108_155815.jpg)
So this allows me to swap Area 2 for Bank 1 or Bank 2 in the upper 64KB of SRAM. I think. BUT I can't work out how to finish the schematic so that ANY other 16KB bank in the upper 64KB can be mapped to Area 2 - at least not without the addition of lots of convoluted circuits and logic chips to force the values of A15 and A14 depending on the output from the 273... but then I don't want to mess with the addressing of normal, non-banked memory space.
![Banging Head |O](https://www.eevblog.com/forum/Smileys/default/bangheadonwall.gif)
So, would anyone be kind enough to give me some explicit guidance on how I need to design the circuit (as simply and with as few chips as possible) so as to expand the address bus to 17 bits and allow me to map any of the 4 banks in the top half of the 128KB SRAM to Area 2 in the lower half of the memory space?
UPDATE: (Edited to update requirements for CP/M 3 compatibility.)
I've been reading through the CP/M 3 system guide (seems I should have done that before I decided the specifications for the MMU
![Face Palm :palm:](https://www.eevblog.com/forum/Smileys/default/facepalm.gif)
) and it appears that CP/M 3 wants the bottom three areas (0, 1 and 2) to be switchable, rather than just the one...
So now I'm looking to have three switchable 16KB banks, Areas 0, 1 and 2, that I can switch the banks in the upper 64KB into and out of at will. I like the idea of being able to map any bank to any area in the memory space, so that's a key requirement for the MMU design now.