Electronics > Projects, Designs, and Technical Stuff
Z80 Single (Perf)Board Computer
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westfw:

--- Quote --- I already identified a suitable 10ns SRAM - the Alliance AS7C4096A which is available in 10, 12 and 15ns variants.
--- End quote ---
Don't you have a supply/logic-level voltage problem?   Your memory chip is 3.3V, and the Z80 is 5V (and supposedly pretty picky about voltage levels?  Or was that the other way around?)

You could take the approach from https://hackaday.io/project/19000 - use RAM only (assuming it works), and use an arbitrarily slow process at startup to copy bootstrap code into the RAM (which is what x86 PCs have been doing for ages, of course.   Fast "rom" is hard to find.)
grumpydoc:

--- Quote from: wilfred on March 28, 2017, 10:20:59 pm ---
--- Quote from: grumpydoc on March 28, 2017, 09:21:56 pm ---Why no Z80 peripheral chips? I hear you ask (OK, maybe I don't)

--- End quote ---

No, you did hear me ask. Thanks for answering. I would (will?) go old school and stick to 4Mhz even though I have a 10MHz CPU on hand. Might try to overclock but it is not a priority. If I was chasing speed I wouldn't be doing it with a Z80. That wasn't part of the experience and hence I'm not nostalgic for it.

--- End quote ---
I have a fair few 2Mhz and 4Mhz parts lying around - CPUs and peripheral chips. But, for some reason, I also found this 20MHz CPU so I wanted to use that, mainly because 20MHz seemed like a challenge.

I also have Flash and 512k SRAM chips lying around although sadly, not in fast enough parts.


--- Quote from: technix on March 29, 2017, 02:33:46 am ---I wonder if you can use some 5V CPLD in socketed PLCC package like EPM7128 or the like. That would replace the sea of standard logic and make your wiring easier.

--- End quote ---

I have nothing against using CPLD's or GALs. In fact one area which is clearly crying out for implementation as a GAL is the address mapping section. However I have no experience with or way of programming a CPLD or a GAL.

The "sea of logic" is not that bad anyway, it fits on the board I want to use and it's only 14 chips for glue logic, plus a latch and buffer.

But I agree if I could program one it would make life easier - especially as there are a couple of things I already don't like about this design. For one thing the reset is very simplistic and I haven't included the Z80 "short" reset logic which guarantees no RAM corruption on reset, nor was I able to include a hardware single step (which needs an extra couple of 7474's), another thing is that the memory mapping is very simplistic and its going to be an absolute pain to do inter-bank moves (which CP/M3 needs).

Of course instead of using a Z80 and a large CPLD I could just use a Z80180 to much the same effect as it integrates the CPU, banked memory SIO, CTC and DMA - or even better the Z80181 (although 100 pin QFP is not overly perfboard friendly).

I might do a Mk II to see if I can squeeze the extra functionality in (although I think that the current project might sate my appetite for building Z80 systems at present).


--- Quote ---I once tried to suggest not quoting an enormous post to add one line that didn't relate to the quote directly. That didn't work. Just making an ironic comment.  ;)

--- End quote ---
+1


--- Quote from: westfw on March 29, 2017, 07:47:32 am ---
--- Quote --- I already identified a suitable 10ns SRAM - the Alliance AS7C4096A which is available in 10, 12 and 15ns variants.
--- End quote ---
Don't you have a supply/logic-level voltage problem?   Your memory chip is 3.3V, and the Z80 is 5V (and supposedly pretty picky about voltage levels?  Or was that the other way around?)

--- End quote ---

The AS7C4096A is a 5v chip although I don't actually plan on using it, I'm going to use the AS6C4008 which is also 5V.


--- Quote ---You could take the approach from https://hackaday.io/project/19000 - use RAM only (assuming it works), and use an arbitrarily slow process at startup to copy bootstrap code into the RAM (which is what x86 PCs have been doing for ages, of course.   Fast "rom" is hard to find.)

--- End quote ---

Yes, I had briefly considered that but it didn't feel "right". I haven't discounted it completely though - especially if trying to integrate more modern interfaces such as USB
obiwanjacobi:

--- Quote from: grumpydoc on March 29, 2017, 08:34:23 am ---
--- Quote from: technix on March 29, 2017, 02:33:46 am ---I wonder if you can use some 5V CPLD in socketed PLCC package like EPM7128 or the like. That would replace the sea of standard logic and make your wiring easier.

--- End quote ---

I have nothing against using CPLD's or GALs. In fact one area which is clearly crying out for implementation as a GAL is the address mapping section. However I have no experience with or way of programming a CPLD or a GAL.

--- End quote ---

This would be a good opportunity to learn. I have used a CPLD and GALs too for the first time in my design and it's quite doable. I used an Altera CPLD (Max II which is 3V3) so you program that in Quartus (check the device support to see what version you'll need) and I used the Atmel WinCUPL to program the GAL, which had a decent manual and examples and was easy enough to figure out. Do test first if WinCUPL runs (Compiles/Simulates) on your system, because on mine (Win8.1) it didn't - I had to go back to an old XP machine...

Another benefit of programmable logic is that you can change it pretty easily. I remember 2 cases in my design that it saved my behind. Simple mistakes can be fixed in the logic or by swapping some pins. Pretty terrific in my book.

Also there are cheap adapter boards available on ebay that go up to 100 pin QFP. Of course you need to be able to solder the 0.5mm pin pitch ICs (flux is your friend)....
grumpydoc:

--- Quote from: obiwanjacobi on March 29, 2017, 08:47:58 am ---This would be a good opportunity to learn. I have used a CPLD and GALs too for the first time in my design and it's quite doable. I used an Altera CPLD (Max II which is 3V3) so you program that in Quartus (check the device support to see what version you'll need) and I used the Atmel WinCUPL to program the GAL, which had a decent manual and examples and was easy enough to figure out. Do test first if WinCUPL runs (Compiles/Simulates) on your system, because on mine (Win8.1) it didn't - I had to go back to an old XP machine...

Another benefit of programmable logic is that you can change it pretty easily. I remember 2 cases in my design that it saved my behind. Simple mistakes can be fixed in the logic or by swapping some pins. Pretty terrific in my book.

Also there are cheap adapter boards available on ebay that go up to 100 pin QFP. Of course you need to be able to solder the 0.5mm pin pitch ICs (flux is your friend)....

--- End quote ---
It would certainly be neat to do GALs at least for projects like this, CLPD might be overkill.

magetoo:

--- Quote from: grumpydoc on March 28, 2017, 09:21:56 pm ---Why no Z80 peripheral chips? I hear you ask (OK, maybe I don't)

--- End quote ---

Why the 65C21 and not the 65C22 VIA which includes timer/counters and "SPI-like" serial?  It could help with I2C interfacing.



--- Quote from: grumpydoc on March 29, 2017, 08:34:23 am ---For one thing the reset is very simplistic and I haven't included the Z80 "short" reset logic which guarantees no RAM corruption on reset,

--- End quote ---

I don't know what the Z80 requires, but since you include an RTC I wanted to mention there are ones that include a reset function with a debounced pushbutton.  It might be cheating, but you can get DS3232 modules on Ebay that includes a battery holder and everything; I'm sure there are plain 8-pin DIP ones too, but I don't have any of those datasheets saved.

If you bring out the handshake lines on the parallel connector, I think you could hang an FT240 there for a USB serial console.  The SBC could just write data as fast as it wanted into the FIFO, not sure if that would work for reading though.  I want to do something like that for a 6502 system, when I get around to it.

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