Electronics > Projects, Designs, and Technical Stuff
Z80 Single (Perf)Board Computer
<< < (4/10) > >>
technix:

--- Quote from: grumpydoc on March 29, 2017, 12:42:03 pm ---
--- Quote from: obiwanjacobi on March 29, 2017, 08:47:58 am ---This would be a good opportunity to learn. I have used a CPLD and GALs too for the first time in my design and it's quite doable. I used an Altera CPLD (Max II which is 3V3) so you program that in Quartus (check the device support to see what version you'll need) and I used the Atmel WinCUPL to program the GAL, which had a decent manual and examples and was easy enough to figure out. Do test first if WinCUPL runs (Compiles/Simulates) on your system, because on mine (Win8.1) it didn't - I had to go back to an old XP machine...

Another benefit of programmable logic is that you can change it pretty easily. I remember 2 cases in my design that it saved my behind. Simple mistakes can be fixed in the logic or by swapping some pins. Pretty terrific in my book.

Also there are cheap adapter boards available on ebay that go up to 100 pin QFP. Of course you need to be able to solder the 0.5mm pin pitch ICs (flux is your friend)....

--- End quote ---
It would certainly be neat to do GALs at least for projects like this, CLPD might be overkill.

--- End quote ---
Well in my 80C88 project the entire bus matrix is implemented in one 100-pin EPM7128 CPLD. There is no sea of standard logic. The EPM7128 is my sea of logic. It takes the entire demultiplexed address/data bus from the processor, emits chip select signals to everything, and have its own internal configuration registers so all slave ports can be assigned dynamically.
grumpydoc:

--- Quote from: technix on March 29, 2017, 02:08:40 pm ---Well in my 80C88 project the entire bus matrix is implemented in one 100-pin EPM7128 CPLD. There is no sea of standard logic. The EPM7128 is my sea of logic. It takes the entire demultiplexed address/data bus from the processor, emits chip select signals to everything, and have its own internal configuration registers so all slave ports can be assigned dynamically.

--- End quote ---
At some point I want to do a 6809 and then a 68k based system. For the former I will probably try to stick with discreet logic, perhaps a GAL or two if I can. For the latter I think I might need something more up market :)


--- Quote from: magetoo on March 29, 2017, 01:40:44 pm ---Why the 65C21 and not the 65C22 VIA which includes timer/counters and "SPI-like" serial?  It could help with I2C interfacing.

--- End quote ---
No more than the fact that I didn't get past the 65C21 as it seemed to do everything I needed.

The SIO has a CTC so that was covered.

I'll peruse the datasheet to see if would be easier to interface to the RTC.


--- Quote ---
--- Quote from: grumpydoc on March 29, 2017, 08:34:23 am ---For one thing the reset is very simplistic and I haven't included the Z80 "short" reset logic which guarantees no RAM corruption on reset,

--- End quote ---

I don't know what the Z80 requires, but since you include an RTC I wanted to mention there are ones that include a reset function with a debounced pushbutton.  It might be cheating, but you can get DS3232 modules on Ebay that includes a battery holder and everything; I'm sure there are plain 8-pin DIP ones too, but I don't have any of those datasheets saved.

If you bring out the handshake lines on the parallel connector, I think you could hang an FT240 there for a USB serial console.  The SBC could just write data as fast as it wanted into the FIFO, not sure if that would work for reading though.  I want to do something like that for a 6502 system, when I get around to it.

--- End quote ---
The Z80 just needs a low pulse at least 3 clocks but if you just do a 1 clock long pulse, low with the rising edge at the start of T2 in an M1 cycle it just clears the PC without doing anything else (so more of a warm start).
technix:

--- Quote from: grumpydoc on March 29, 2017, 03:14:39 pm ---
--- Quote from: technix on March 29, 2017, 02:08:40 pm ---Well in my 80C88 project the entire bus matrix is implemented in one 100-pin EPM7128 CPLD. There is no sea of standard logic. The EPM7128 is my sea of logic. It takes the entire demultiplexed address/data bus from the processor, emits chip select signals to everything, and have its own internal configuration registers so all slave ports can be assigned dynamically.

--- End quote ---
At some point I want to do a 6809 and then a 68k based system. For the former I will probably try to stick with discreet logic, perhaps a GAL or two if I can. For the latter I think I might need something more up market :)

--- End quote ---
If you are doing a 68k system, just forgo the MC68HC000 and go straight to a MC68LC040/MC68882/FPGA combo. This combo runs at 3.3V so you can use newer FPGAs. MC68882 is a better FPU than the one came with the '040, and it is easier to find LQFP 'LC040 than '040 anyway.

Since the 'LC040/'882 combo is a full 32-bit system with MMU, you can build a DDR DRAM controller into the FPGA that accepts a single standard SODIMM memory stick. 2GB should be enough for most applications, and used 2GB DDR3-1600 SODIMMs should be fairly cheap to find.

If you want to reduce the amount of IP core types (aka licenses) you can use this three-IP solution: the aforementioned DDR DRAM controller, a quad-SPI XIP Flash controller, and a PCI Express root complex with 24 lanes configured in x16/x4/x1/x1/x1/x1. The quad-SPI core supplies the CPU with a firmware. The PCIe controller allows you to use COTS graphics (a GPU occupying the x16 lane,) storage (an NVMe SSD occupying the x4 lane,) audio (sound card occupying a x1 lane, also the HDMI/DP audio output on the GPU,) USB (a USB 3.1 chipset occupying a x1 lane,) wired (Gigabit Ethernet occupying a x1 lane) and wireless networking (Wi-Fi occupying a x1 lane, Bluetooth over the USB chipset)

As of software, the '040 definitely warrants a full Linux distribution. The firmware can be built from U-Boot chainloading UEFI. U-Boot for better low level initialization capability and UEFI for better expansion bus support (especially when PCIe is involved.) The kernel and initrd can be loaded from the SSD, with an OpenFirmware device tree embedded in the firmware. Thanks to the GPU you can have 3D accelerated graphics from the get-go. Video playback can also be delegated to the GPU so the '040 is not choking.
grumpydoc:

--- Quote from: technix on March 29, 2017, 05:24:17 pm ---If you are doing a 68k system, just forgo the MC68HC000 and go straight to a MC68LC040/MC68882/FPGA combo. This combo runs at 3.3V so you can use newer FPGAs. MC68882 is a better FPU than the one came with the '040, and it is easier to find LQFP 'LC040 than '040 anyway.

--- End quote ---
I can aim that high but I think you overestimate my abilities, not to mention time available :).

There would be a definite walk before run element to any ambition for a system that powerful - perhaps when I retire so I have unlimited time to play.
daybyter:

--- Quote from: grumpydoc on March 29, 2017, 12:42:03 pm ---It would certainly be neat to do GALs at least for projects like this, CLPD might be overkill.

--- End quote ---

For GALs, you need a programmer like the tl866cs? And most GALs are EOL long ago? For Xilinx CPLDs, there are cheap parallel port cables to program and there are 5V versions available (also EOL, though).

Another option are those cheap FPGA boards:

http://www.ebay.com/itm/ALTERA-FPGA-Cyslonell-EP2C5T144-Minimum-System-Learning-Development-Board-/401255830236?var=&hash=item5d6cb612dc:m:m-tMy5MOZfxAvfiGVkWVMGg

I'm playing with such a board (for a c64 z80 module) and it's a great way to learn about the fpga technology, methinks.
Navigation
Message Index
Next page
Previous page
There was an error while thanking
Thanking...

Go to full version
Powered by SMFPacks Advanced Attachments Uploader Mod