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Z80 Single (Perf)Board Computer

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grumpydoc:

--- Quote from: wilfred on March 29, 2017, 11:40:21 pm ---
--- Quote from: grumpydoc on March 29, 2017, 12:42:03 pm ---It would certainly be neat to do GALs at least for projects like this, CLPD might be overkill.

--- End quote ---
I'm interested in the use of GALs if you decide to consider it. Although any design you make available will be more generally useful without them just because they are obsolete. I think you'd have to one with TTL chips and then show how it could be done with a GAL.

--- End quote ---
Well, Mk I will be using discreet TTL as I'm not going to revisit the design much now, Mk II could wind up using programmable logic but would probably be based on a Z80182 which will remove the need for a lot of the glue logic anyway.

grumpydoc:

--- Quote from: grumpydoc on March 29, 2017, 03:14:39 pm ---
--- Quote from: magetoo on March 29, 2017, 01:40:44 pm ---Why the 65C21 and not the 65C22 VIA which includes timer/counters and "SPI-like" serial?  It could help with I2C interfacing.

--- End quote ---
No more than the fact that I didn't get past the 65C21 as it seemed to do everything I needed.

The SIO has a CTC so that was covered.

I'll peruse the datasheet to see if would be easier to interface to the RTC.

--- End quote ---

Having read the 65C22 datasheet I am not sure that the serial interface capability will be that useful. The problem is that the 6522 was designed to be a 6502 peripheral and the PHI2 input is expected to be the CPU phase 2 clock - i.e a fixed period square wave.

In a Z80 design we are making use of the fact that the really important thing about PHI2 is the rising edge so if we apply an active high pulse when we want to read or write the chip registers it will still work - but it makes PHI2 completely useless as a timing source - which is pretty much what the timers and shift register want to do with it.

Having said that I was hopeful initially that I could implement a hardware single step function if I used a 65C22 - basically the way this works is that you set up the registers either with an initial state or with the state saved at the last breakpoint or single step, toggle a bit on an output latch which enables a hardware counter triggered on M1 and then execute a return.

After a set number of opcode fetch cycles (however many it takes to complete restoring the registers, plus the return, plus the first M1 of the following instruction which is the one you actually want to execute) you pull \$ \small \overline{INT} \$ or \$ \small \overline{NMI} \$ low**. the Z80 finishes executing the current instruction and takes the interrupt - whereupon you give control back to the console, print the registers or whatever.

As I can't squeeze in the extra flip-flops to make the counter I got quite interested in the fact that timer 2 can be set to count input pulses on PB6 until I noticed this comment "The decrement pulse on line PB6 must be Logic 0 during the leading edge of the PHI2 clock" - so it is still using PHI2 to drive the counting, not just the falling edge of the pulse on PB6, so I can't just route \$ \small \overline{M1} \$ to PB6 and use the counter to count instructions.

I briefly thought that I could drive PHI2 from \$ \small \overline{\overline{M1} \land \overline{IORQ}} \$ and drive CS2B from \$ \small \overline{IOB_2} \$ thinking that I could count M1 pulses by applying them continuously to PIH2 - plus applying a pulse when \$ \small \overline{IORQ} \$ is active for when we want to talk to the chip.

However I don't think that will work out - doing so will mean that the rising edge of PHI2 will almost certainly arrive before the chip is enabled by a high on  CS2B and I won't be able to access it correctly/at all.

So, at present, I can't see an advantage in using the 65C22 over the 65C21.

** - well, \$ \small \overline{NMI} \$ really as it is better suited to this task being edge triggered and not (potentially) having a complex acknowledge cycle. You could use \$ \small \overline{INT} \$ but it would be painful to do so, I think.

grumpydoc:
So, quick update.

I know building Z80 systems is a minority sport but I'm enjoying designing this so I hope that you don't mind indulging me.

I thought I'd finished the layout etc. but when ordering parts realised that I had made a small mistake - I had used a 3-input OR gate to generate chip select for the ROM but placed a 74xx27 which is a 3-input NOR gate. Turns out that there isn't a TTL triple 3-input OR gate, there's one in the original CMOS CD40xx set but the fastest available is HC(T) which is probably a bit slow for this build. So I'm going to have to cascade 2 x 2-input OR gates to do that.

That meant I could take a package off the board and looking at the layout again I realised I could squeeze a couple more in if I was a bit less conservative about leaving space for power rails.

Consequently I have room for a hardware single step and thought it was worth showing how this works - I can't claim any credit for this as it is totally ripped off from the Nascom 2.

This is the circuit



It works as follows - following reset FF1 is clear so the default state is with the STEP input low and the Q output of FF1 also low - in this condition M1 pulses are applied to the clear input of FF4 hence \$ \small \overline{NMI} \$ is held high. The set inputs of FF2 and FF3 are held low hence their outputs are high and input clock pulses to these two flip-flops are ignored.

To step a single instruction the code sets up all the registers with the stored contents from the last breakpoint then executes the following

   push    af
   ld      a,8      ; Toggle the "STEP" line high
   out     (0),a
   pop     af
   retn


The timing is then:



NMI is pulled low with the rising edge of the first M1 cycle of the target instruction, the falling edge of NMI resets FF1 and allows M1 to reset FF4 with the next low pulse. The processor takes the interrupt at the end of the target instruction.

It's quite neat.

grumpydoc:

--- Quote from: wilfred on March 31, 2017, 11:46:40 pm ---Your high speed ideas are little outside my approach of choice but ideas like this are welcome.

--- End quote ---
I wouldn't see any problem with the slower parts and the same schematic.


--- Quote ---Is there a link to the location of the Nascom 2 info?

--- End quote ---
http://www.nascomhomepage.com/

Lots of useful info and programs there

Also http://80bus.co.uk.mirror.jloh.de/pages/magazines.htm for the newsletters and club magazines - in fact the home directory of that site also has some useful stuff.

http://www.cpm.z80.de/ is  worth a browse as well.

grumpydoc:
Final (I hope) layout



This would be so much better on a PCB although I want to make sure that it works first, I need to have another go at learning some EDA tool, not sure which though. Free Diptrace is probably too restricted (this design is well over 500 pins, for instance), I tried KiCad and could not manage the odd UI and I wasn't that impressed with gEDA though did stick with it for longest as I managed to hack some of the PCB layout tools a bit.

Does anyone have any suggestions?

All the bits now ordered. That was rather...................... expensive, much more than I'd anticipated.

Partly because I always order at least twice as many items as I need on the basis that "they will be useful in the parts box". I'm slowly realising this is mostly a fallacy but the odd thing does prove useful once in a while so it's hard not to do it. The problem is figuring out which 5% of what I bought but did not immediately need will turn out to be useful.

Partly, some items just were quite steep, especially the PIA and SIO.

I also keep forgetting just how much saying "I'll use some nice turned-pin sockets for this projects" adds to the cost, not to mention headers, batteries, etc which are really not that cheap in small quantities.

With luck I should find time to put it together after Easter.

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