EEVblog Electronics Community Forum
Electronics => Projects, Designs, and Technical Stuff => Topic started by: raphael3215 on August 19, 2024, 05:49:29 pm
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Hello, This is my first time writing to a forum, so apologies for any mistakes. I've been designing and testing a homebrew Z80 computer, and I finally decided to attach the PIO chip for parallel input/output. I've come to a question about the design of the PIO which I have not found an answer in any of the documentation, and it is regarding the Strobe input in the ports. As far as I understood, every output in mode 0 of the PIO must have its data acknowledged by pulsing low the given port strobe when the device has finished reading the port. This is supposed to generate an interrupt, if enabled. Now, I assumed that, if the handshake is not made, the PIO would just ignore subsequent writes to it until the handshake is made, but that is not what I have observed. By setting the line low or high, the PIO latches any data that it is sent to it. Is there any documentation regarding this behavior, or am I messing something up?, is the strobe only purpose to generate an interrupt and it doesn't interfere in the data latching?
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Well, the manual says "Ready stays active until the positive edge of the strobe is received, indicating that data was taken by the peripheral." It doesn't say anything about timing out, or giving up - only that it sits and holds READY until it sees a rising edge on STROBE# to acknowledge receipt. If your device never acknowledges the more reasonable assumption (which I think you checked) is that it will sit there waiting forever, or until cleared by software.
Clearly this is intended for asynchronous transfer to a peripheral.
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Yes, I observed that, I will check the ready line with the scope later when I get home but it seems then my thoughts were incorrect in the working of the PIO strobe. Thanks for the answer.
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Possibly you've been looking at a different revision of the documentation.
ZILOG Z80 PIO USER'S MANUAL (http://www.z80.info/zip/z80piomn.pdf) has (on page 10):
Selecting Mode 0 enables any data written to the port output register by the CPU to be enabled onto the port data bus. The contents of the output register may be changed at any time by the CPU simply by writing a new data word to the port. Also the current contents of the output register may be read back to the Z80-CPU at any time through the execution of an input instruction.
With Mode 0 active, a data write from the CPU causes the Ready handshake line of that port to go High to notify the peripheral that data is available. This signal remains High until a strobe is received from the peripheral. The raising edge of the strobe generates an interrupt (if it has been enabled) and causes the Ready line to go inactive. This very simple handshake is similar to that used in many peripheral devices.
Disallowing further writes to the output latches till READY had been acknowledged by STROBE would have prevented Mode 0 being used for simple output without any handshaking + would have added silicon complexity and the need for extra bits in the mode word to determine whether or not handshaking was required. The designers chose not to do that, and simply settled for providing an interrupt, leaving it up to the programmer to manage the sequencing for handshaked data transfer or ignore it for simple bit-banged output.
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I just looked at the datasheet at https://www.zilog.com/docs/z80/ps0180.pdf (https://www.zilog.com/docs/z80/ps0180.pdf)
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The data sheet says it latches to the output register on WR#. But nothing about updating it with additional writes. Isn't mode 3 for bitwise GPIO?
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Yes, this is definitely a different version from what I was currently using, thanks a lot for it, this answers my question perfectly. The bit banging part also makes sense, I implemented a simple driver for a 1602 LCD using the 4 bit control mode using a d-latch and I was thinking I would have to build an additional circuit just for providing the strobe for the PIO, glad for now it is not the case for now . Thanks everyone again for the help
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As far as I read, the strobe signal is completely ignored in mode 3
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As far as I read, the strobe signal is completely ignored in mode 3
That's how I read it as well.
I *suppose* the designers could have made bit-banging in mode 0 impossible by gating writes to the output latch as you initially expected, leaving mode 3 as the only bit-bang capable mode, but that would have needed more silicon, in an era when designers still taped out their IC layouts by hand considering the cost of every extra gate.
See https://en.wikipedia.org/wiki/Rubylith
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My still only remaining doubt is that, if a rewrite happens without the strobe, will the ready line go low then high again during the rewrite, as in, any indication that the data is changing, I'd assume yes, since it has a delay for the write to happen where the port is not ready for reading.
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Also, the PIO doesn't have a WR# line, only a RD#, How does It receive then the WR# from the CPU?
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As far as I read, the strobe signal is completely ignored in mode 3
That's how I read it as well.
I *suppose* the designers could have made bit-banging in mode 0 impossible by gating writes to the output latch as you initially expected, leaving mode 3 as the only bit-bang capable mode, but that would have needed more silicon, in an era when designers still taped out their IC layouts by hand considering the cost of every extra gate.
See https://en.wikipedia.org/wiki/Rubylith
Since they have to hold READY there's already a flip-flop for it presumably (or an SR latch/JK or something). And since neither READY or even WR# to the holding register are used in some modes (e.g. input), there's probably already a bit of logic around it? Who knows what that looks like... maybe it ends up masking WR# if READY is held active.