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Repair / Re: SIP compressor won't start?
« Last post by amyk on Today at 02:25:17 am »
Open its output to the atmosphere so that you're not feeling the force of compression, and see if it's still difficult to turn. I recommend checking the cylinders for roughness.
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Beginners / Re: Difference amplifier
« Last post by jim_griff on Today at 02:19:08 am »
I'm sure you know what "gain" is - the amplification factor between input and output. Output/Input = Gain factor.

Common Mode Signal:
A signal that is exactly the same on both inputs.

Differential Mode Signal:
A signal that is exactly the opposite ("different") on both inputs. i.e. You could have a sinewave that is inverted on the 2nd input. The sinewave is 100% differential, 0% common.

A common mode amplifier will use addition. Anything that is different will be suppressed through that addition of signals. Anything that is the same will be added together and amplified. If you add +1 to +1 you get 2. If you add -1 with +1 you get 0. Differential mode signals are cancelled out.

A differential amplifier subtracts input signals from one another. If you subtract -1 from +1 you get 2. If you subtract +1 from +1 (common mode), you get 0.

Differential mode signals are very useful for EMI suppression which is common mode by nature. i.e. EMI will usually affect two wires in almost exactly the same way. So if you are to send a +signal (noninverted) and -signal (inverted) together down two wires into a differential receiver, any EMI that's common mode should be suppressed as it gets cancelled out.

Of course, it's a lot more complex than that, and involves a lot of complex impedance calculations.
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Test Equipment / Re: HP Logic Analyzer Inverse Assemblers
« Last post by MarkL on Today at 02:16:34 am »
The opcode fetch is a faster cycle than a regular memory fetch.  Below is the opcode fetch timing cycle without the wait states.  The first byte of the instruction is sampled by the CPU on the second rising edge of PHI after /MREQ falls.  In rough numbers, this allows 1.5 clock periods for access time.

A memory data read is sampled by the CPU on the second falling edge of PHI after /MREQ falls, allowing it roughly 2 clock cycles for access time.

Since the opcodes and operands necessarily share the same physical memory in the Z80 architecture, they therefore have the same access speed requirements.  The system must be designed to support the higher speed of the opcode fetch cycle.

So, LA slave sampling on the rising edge of PHI, with only 1.5 cycles of access time, should always work for memory.  I suppose it's possible that a Z80 system could be designed with slower memory that is only for data and never instructions, but I've never seen that.

However, in the case of an I/O read, the cycle time is roughly 2.5 cycles, and starts on a rising edge of PHI, which is later in phase than an opcode or memory cycle.  See I/O timing below (the "Tw" in the diagram is an automatically inserted wait state).  If the LA slave was sampling only on the rising edge of PHI, the peripheral read would have only 2 cycles to settle.  Giving it an extra half cycle to settle is probably not going to make a difference since peripheral registers, etc. are generally much faster to access than memory, but it would be wrong to assume this is always the case.

I think I'm convinced sampling on both edges of PHI is the right thing.
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Just training of DDRx memory interface can take several seconds all by itself depending on the interface and DDR revision. The only realistic way of achieving boot times anywhere close to requested is a suspend-to-RAM, but that requires uninterrupted power supply to preserve it's contents.
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Quote
inserting anything but a drill bit into a drill chuck.
And whats wrong with that?
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Test Equipment / Re: SDS800X HD Bugs/Wanted Features
« Last post by electronics hobbyist on Today at 01:54:32 am »
Save button does nothing in the Bode plot, it should make the usual screenshot.
Which file format and to Internal or USB ?

Save image based on Bode Plot print settings.
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Test Equipment / Re: Hacking the Rigol DHO800/900 Scope
« Last post by AceyTech on Today at 01:52:13 am »
Edit: a 35*35 mm² heatsink (with less than 35 mm height, I assume?) will be far from 1 K/W -- more like 10 K/W. You would need a much more hefty heatsink to passively cool the DHO.

On closer examination;  While that SBC itself is fanless, their temp spec says "@0.7m/s Air Flow".,   BTW it looks  significantly shorter than 35mm height.  They also don't have a FPGA running balls out, contributing to the heat load.

Incidentally, this is a very warm product, naturally.  Uncomfortably so, IMHO.  When I unplug a USB connector it's HOT., BNC's are as well.  I forgot to measure the temperature on the connectors during my fan testing, but the last mod I did cooled the I/O's considerably.

BTW: @shapirus
I watched that video you mentioned, and have some issues with his methodology.  I'm not saying it was flawed per se', but I just can't put much confidence in some of his findings in general.  Ex: when Rigol did their HALT testing, I doubt they turned it up on end, dumping heat into the power supply section.
  -From what I've observed, these scopes don't really need much of an excuse to reboot.  Sometimes, I'll look over at my DHO because it's clicking and flashing in the middle of a reboot cycle.  For no reason!
(Before anyone asks: ^that's before I opened it)
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At the input is an RC differentiator (R2-C3) that I found out is required, since the NE556 one-shot will not terminate while the input is left low.
But your circuit shows that the input (to the 556) is pulled low (to zero volts) by R2.
Where is the zero-volt reference on the your scope trace? To me, it looks like the input to the chip is being driven negative by a volt or more, it then settles-out at about -0.6v (one silicon junction voltage drop below zero volts). I would suggest that the 1.5mS is the time it takes for the chip to recover from having its inputs forced below the zero (ground) reference.

The minimum you need to do is change R2 to pull-up to Vcc such that the chip is not permanently triggered. You might then consider some means of preventing the input from exceeding Vcc (which might also have a negative impact on the chip).
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So you would have a certificate on the server, preferably not self-signed.

Can you explain what the advantage of having it not self-signed is?
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Even if LM337 or the transistors were wired wrong, there is a 2.5 kΩ resistor in the path. With 35 V directly across it, the current is limited to 14 mA. Power on this 120 Ω resistor is below 25 mW. Something is not adding up in that description.

As for wiring: make sure LM337 is connected right. The component is very similar to LM317, but their pinout is different. TO-220 package for LM337 has input and output pins swapped compared to LM317.
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