Recent Posts

1

Repair / Re: Which USB3-SATA dock/cradle/adapter for 3.5+2.5" hdds without 4K/sec emulation?

« Last post by fzabkar on Today at 11:37:00 am »

There is no such thing as a "good dock" or a "bad dock". Some will present a fixed 512-byte physical sector size to the USB host while others will present a fixed 4KB physical sector size. Still others will use 512-byte sectoring for drives with a capacity less than 2TiB, and automatically switch to 4KB sectoring for drives larger than 2TiB.

The reason for this behaviour is so that large drives can be used with legacy OS-es such as Windows XP. Since Win XP is limited to MBR partitions, the maximum number of sectors it can address is 2^32. At 512 bytes per sector, that works out to a capacity of 2TiB. However, if the sector size is increased to 4KB (= 8 x 512B), then XP can see a USB mass storage device with a capacity of 16TiB. This was how Seagate approached this problem with their early external drives. WD's My Book externals can be "fast formatted" to present either sector size to the host.

Note that these USB bridges behave the same way whether the drive is a 512n (native) or 512e (emulated) model. That is, it has nothing to do with whether the drive is an Advanced Format model with 4KB physical sectors.

2

Projects, Designs, and Technical Stuff / Re: (Yet Another) DIY Multislope ADC

« Last post by NNNI on Today at 11:36:33 am »

iMo: Thanks for taking the time to try and understand my design and work with it, it definitely helps a lot to have an outside perspective for new ideas and improvements. As diminddl already mentioned, the repository was essentially left as such after the last set of experiments in June/July 2023, so there are a lot of things unfinished and not properly documented. I am trying my best to finish up my existing project backlog (among other things) and hope to get back to it in a few months.

kleinstein: Thanks for the insight regarding jitter and its effects on a multislope ADC.

PCB.Wiz: Once again, thanks for providing more information regarding low-jitter clock sources. This is something I will be looking at in the future.

Regarding rundown - the previous 'test' version of this ADC did have a rundown phase implemented in PIO (see image attached) based on this paper: https://dspace.mit.edu/bitstream/handle/1721.1/84880/868678609-MIT.pdf?sequence=2. I had banding issues with that ADC as well. You can find the code here: https://github.com/NNNILabs/6.5-Digit-Multislope-ADC/tree/main/Multilslope%20IIA

3

Projects, Designs, and Technical Stuff / Re: (Yet Another) DIY Multislope ADC

« Last post by iMo on Today at 11:34:54 am »

Here is my naive attempt with rundown..
Not sure one instruction there even exists , not sure it would work, I cannot test it (no analog part here), but it fits into 32 instructions.. So an experienced person has to finetune it..
The polarity of the COMP and PWMA and PWM need to be adjusted accordingly..

Code: [Select]

.program ms
.side_set 1
; 1 side set bit for the MEAS pin

; don't forget to enable auto push
start:
    set pins, 0         side 0
    mov X, !NULL        side 0              ; set X to 0xFFFFFFFF
    out Y, 32           side 0              ; read the number desired counts
    irq 0               side 0              ; first residue reading
    out NULL, 32        side 0              ; stall until DMA finished reading the ADC

beginning:
set pins, 1         side 1
jmp pin pwmhigh     side 1
set pins, 2         side 1 [15]
jmp Y-- beginning   side 1 [13]
jmp finish          side 0

pwmhigh:
jmp X-- dummy       side 1 [15]
dummy:
    nop                 side 1 [11]
set pins, 2         side 1
jmp Y-- beginning   side 1
jmp finish          side 0

finish:
    ; HERE THE RUNDOWN STARTS, SIMPLY GO TOWARDS ZERO VOLT AND COUNT CLOCKS (results in X or Y)
    ; set pins, 0         side 0              ; turn both PWMA/PWMB switches off
    in  X, 32           side 0              ; push PWM to FIFO, after the push X=0, Y=0
   
rundown:
    jmp pin godwn       side 0
    set pins, 1         side 0              ; if COMP==0 set PWMA/PWMB polarity towards zero volt
   
goup:
    jmp pin AuxADC2
    jmp X-- goup        side 0
   
godwn:
    set pins, 2         side 0              ; if COMP==1 set PWMA/PWMB polarity towards zero volt
godwnl:
    jmp !pin AuxADC2
    jmp Y-- godwnl

auxADC2:
    set pins, 0         side 0              ; turn both PWMA/PWMB switches off
    in  X, 32           side 0              ; push X to FIFO
    in  Y, 32           side 0              ; push Y to FIFO
   
    irq 1               side 0              ; second residue reading
    out NULL, 32        side 0              ; stall until DMA finished reading the ADC

.wrap_target
dither:
    jmp !OSRE start     side 0              ; jump out of desaturation when the OSR has data
    set pins, 1         side 0              ; set pin polarity
    jmp pin dither      side 0              ; check if the integrator is still high
    set pins, 2         side 0 [1]
.wrap


4

FPGA / Re: State machine design choice

« Last post by nctnico on Today at 11:34:22 am »

When dealing with complex sequential logic in an FPGA, it can help to use a programmable state machine. This can even be in the form of a small processor like Picoblaze / Pacoblaze. The latter can be programmed using a simple assembler. The program for a programmable state machine can be generated using a program or script (Python).

Looking at the problem at hand, using a shared sub-statemachine which does the transmission seems to be the easiest way to go. It looks like there are 3 parallel processes (A, B and C) and 1 send/receive process. So each process creates a packet, waits for the transmission statemachine to become available (make sure this works in a round-robin fashion so in case one of the processes gets stuck, the others still can send/receive), hands over the data to the transmission state machine once it becomes available, waits (or timeout) for the answer to arrive and continue with the rest of the processing.

5

Test Equipment / Re: Hacking the Rigol DHO800/900 Scope

« Last post by Fungus on Today at 11:33:43 am »

btw, this skew thing should be in bug report thread, not here.

We don't know if it's a bug or a curiosity yet.

It's not a hack though, I'll give you that.

6

Beginners / Re: hFE of a NPN transistor

« Last post by tggzzz on Today at 11:33:00 am »

h_FE varies between transistors; manufacturers usually specify minimum and typical values.

For any given transistor, h_FE varies with I_C, frequency, and probably other parameters such as temperature.

Hence circuits are designed so they are tolerant of variations in h_FE.

Identical transistors, either manually selected and thermally connected, or on the same silicon die will have h_FE that tend to track each other.

7

Buy/Sell/Wanted / Re: wtb: Delock-95000, miniPCIe-sATA-quadport-HBA (want to buy/where to buy)

« Last post by Nominal Animal on Today at 11:31:59 am »

If you find each other so aggravating you cannot interact in a mutually beneficial way, just ignore each other.

And remember, you do not know each other: all you know is the other's written output.  It is a very narrow-bandwidth communications method compared to face-to-face and voice, with estimates ranging up to 90% of cues and subtext in face-to-face communication being nonverbal.  This is also something everyone can work on, without it being anything personal: we do not simply "express" ourselves here, we are trying to convey information, questions, answers, so adjusting the output formatting to ensure mutually beneficial communications is the rational thing to do here.

When one feels one needs to voice out ones opinion/view/experience on someone elses output, just venting is not useful.  What would be useful, would be to point out exactly what it is that hinders communication the most; preferably in a format that helps others understand the issue, and compensate if possible.

I wrote the why writing style and grammar matters in the Beginner forum (now sticky), because it makes a huge difference.  One benefits the most from understanding widely different viewpoints, which is what makes communicating contrary views, and most importantly the reasons and basis for those views, so extremely useful.  It is not about "being polite" or "being professional"; fuck that.  It is about getting the maximum mutual benefit out of technical discussions.

8

Beginners / Re: defective supercap?

« Last post by coromonadalix on Today at 11:28:53 am »

charging a supercap can take a very long time,  in some case it will appear as a dead short

i usually use them in clock related stuff  or clock backed up  mcu  etc ...   i use an resistor  to drop the inrush it create,  sure it create a time constant, a simple diode and a resistor on the clock ic  ....

for an 1.5 farad at 5v   it take at least 15 mins to charge it,  and keep 1 week of clock

10 farad is a lot ... i mean a lot  loll



for sure    you don't use that to filter out an psu  ??

9

Programming / Re: Show definitions + autocomplete function parameters for C (text editor over ssh)

« Last post by 5U4GB on Today at 11:27:52 am »

Another option if you don't want to get into X for opening edit windows on remote systems is to use an SSH client that allows local file editing of remote files, so it copies the data across, allows local editing with the editor of your choice, and then copies it back again when you save.  In effect it allows local editing of remote files.  I believe MobaXterm allows this.

10

EEVblog Specific / Re: EEVblog 1610 - Deye Hybrid Solar Inverter

« Last post by Phoenix on Today at 11:26:46 am »

Your comment about the MOSFET packages around 15min - they look like a custom mounting bracket that allows a single screw to apply pressure to two TO-247 packages. It's not a special package.