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Projects, Designs, and Technical Stuff / Re: Target PDN impedance for analog circuits
« Last post by T3sl4co1l on Today at 01:02:03 am »Idunno about that; 5Ω at 1GHz is 0.8nH. Even a small DFN with multiple parallel power pins, struggles to get that low from parallel bypass caps thru pads, pins and bondwires to the die. At some point we have to assume good enough will do, or that the IC has solved some of these issues itself (onboard bypass?).
But that's also something like a 0.5ns step, let alone CW, so you're going pretty fucking fast there.
Also depends if it's class A; obviously it can't be in this example (Io(pk) > Icc) but for smaller signals it could, and then Vcc and Vee act in parallel, which helps. In an extreme case, we might have a choke supplying an MMIC, or PP transistor amp, etc., and Icc is explicitly steady over a cycle; it's no accident LC-coupled RF amps are a popular choice (or perhaps the only option), heh.
Tim
But that's also something like a 0.5ns step, let alone CW, so you're going pretty fucking fast there.
Also depends if it's class A; obviously it can't be in this example (Io(pk) > Icc) but for smaller signals it could, and then Vcc and Vee act in parallel, which helps. In an extreme case, we might have a choke supplying an MMIC, or PP transistor amp, etc., and Icc is explicitly steady over a cycle; it's no accident LC-coupled RF amps are a popular choice (or perhaps the only option), heh.
Tim