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FPGA / Re: If Lattice iCE40UltraPlus has DDR primitives like ODDR in Xilinx?
« Last post by SiliconWizard on Today at 08:03:13 am »I don't think they do. Haven't seen any mention of that in the datasheet nor in other docs.
And keep in mind these are cool, but relatively "slow" devices. I/O buffers are rated 250MHz max. (Above 2.5V for outputs, less otherwise.)
So if you're hand-implementing DDR, your data rate may be much lower than you'd otherwise expect from DDR RAM. That said, its logic blocks wouldn't take high enough Fmax for it to make a difference anyway.
Using DDR RAM with an iCE40UP sounds a bit odd - what's your use case?
And keep in mind these are cool, but relatively "slow" devices. I/O buffers are rated 250MHz max. (Above 2.5V for outputs, less otherwise.)
So if you're hand-implementing DDR, your data rate may be much lower than you'd otherwise expect from DDR RAM. That said, its logic blocks wouldn't take high enough Fmax for it to make a difference anyway.
Using DDR RAM with an iCE40UP sounds a bit odd - what's your use case?