Electronics > Power/Renewable Energy/EV's

2kW Boost PFC blown up....how?

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Faringdon:
Hi,
EDIT....This post is not worth reading if you are seeking interesting power supply issues....this problem was caused by poor PCB layout......the blow up problem has now been solved by increasing soft start cap and more importantly, by increasing the fet gate series resistor......doing that reduced the switching transition noise, which "covered up" the poor PCB layout to an extent........END OF EDIT}
Just tried initial mains powering of 2Kw Dual Boost PFC with UCC28070A. Only 7W load. Mains input fuse 3.15A.
FETs  = 600V (SiHG186N60)
Sic output diode. (C6D0465A)
First did inrush via 47R….no problem….
…Then enabled PFC stages….input fuse blew immediately. Didn’t see any rise in Vout.
Current sense peak maximum threshold  is set well below inductor saturation level.
Duty cycle of UCC28070A is set to 0.9 maximum.
CSTs are 50:1
Cout = 540uF.

UCC28070A datasheet
https://www.ti.com/lit/ds/symlink/ucc28070a.pdf?ts=1659614618238&ref_url=https%253A%252F%252Fwww.google.com%252F

On  examination, both FETs are short G-D-S. Nothing else on the board is damaged (other than input fuse). Gate drives still working fine.
Suspect problem   due to either…
1…..Much stray inductance in the FET current sense transformer output circuit. This could have caused the BAS16 current sense rectifier diode (75V) to blow given that reset Zener is 68V. Also, it’s a distance of some 15cm from CST to the burden resistor which is near the PFC  controller……..so stray inductance ringing in this may have wadgered the current sense signal? (even though I have a 1k/470p filter on the way to current sense pin).
2…….Ringing on the 650V Boost FET Drain……there are no snubbers on the boost FETs. I have simulated stray inductance in the FET/DIODE/Cout wiring, and I cannot get it to ring above 600V, so I doubt that there was ringing above 650V on the Boost FET?

For the next power up, I will…..
a…..Set the UCC28070A max duty cycle to 0.1.
b……Take the current sense burden resistors off the PFC controller board, and bring them much nearer the CST (I have blank footprints there  ready for them).
c……Introduce the “slope compensation” ramp signal, which I had previously unpopulated.
d….Add  RC snubbers to the Boost FETs.
e….Change the PFC disable/enable signal so it grounds the soft start input, instead of the current sense error amplifier outputs.
f…..Use 1200V FETs for the next power up.
___---___
The disadvantage of (b) above is that the current sense signal will now be going some 15cm back to the PFC control board…..however , this seems better than sending the CST output current that far.

I’m also wondering if the FETs have been mis-handled and have ESD damage? Also, they came from Farnell in a clear plastic tube (as attached)…..this therefore cannot be ESD safe? Its possible these FETs may have been ESD weakened, and making then switch mains killed them off?

wraper:
That is a cut to length piece of tube in which they come from the factory. As long as it is put into ESD shielding bag, it's a proper way how to package them. Although I don't think that tube is intended to shield from static discharge as such, it's unlikely ESD will shot through due to its thickness. Nor power MOSFETS are particularly sensitive to ESD. They have large gate capacitance and often TVS diode between its gate and source.

Faringdon:
Thanks, when the staff cut these tubes up, they have to handle the FETs, and i wonder if they do so with proper ESD precautions?...i mean, they probably all wear these trainers, with their rubber souls, which will give static zaps to anything they touch aswell?

I also noted that this FET does not have the bidi TVS from gate to source...
SiHG186N60 FET datasheet..
https://www.mouser.co.uk/datasheet/2/427/sihg186n60ef-2897279.pdf

Must admit ive had several TO247 SIC 1200V NFETs  (as used in a 300W, 300-100V Buck SMPS) go short on me from me handling them without ESD protection in an electronics lab. (not even powering them up)
Also, the gate to drain capacitance of this SiHG186N60  fet is only 5pF.

wraper:

--- Quote from: Faringdon on August 04, 2022, 01:32:58 pm ---Thanks, when the staff cut these tubes up, they have to handle the FETs, and i wonder if they do so with proper ESD precautions?...i mean, they probably all wear these trainers, with their rubber souls, which will give static zaps to anything they touch aswell?

--- End quote ---
I'm pretty sure farnell has proper ESD precautions implemented. Chances that your issue is from Farnell side is nearly zero.

--- Quote ---I also noted that this FET does not have the bidi TVS from gate to source...
--- End quote ---
The fact you don't see it in datasheet does not mean there is none. Quite likely there is none but often it's just not mentioned.
Also if you don't want something like this not to blow on first power on, you should use protection. Like a high power incandescent bulb or iron for clothes in series with mains.

Faringdon:

--- Quote ---I'm pretty sure farnell has proper ESD precautions implemented.
--- End quote ---
Thanks, Maybe 40 years ago i would have agreed, but  the UK now is virtually devoid of electronics, it all having been outsourced to the Far East, so nobody could blame Farnell if they have a lack of electronics knowledge within their ranks.....AYK, it comes with the "outsourcing" territory unfortunately.
I have worked in a very good number of (small) electronics co's in UK which do not have any ESD precaution at all....even working on static gen carpets......these are small co's doing bits of government grant funded projects. (As such because  few woudl invest in an electronics project in uk now, for fear of being gazumped by a Far Eastern product.)

There are token UK projects in electronics, which give a co the "designer/manuf" status they need in order to be given the middle man importer-of-electronics jobs, which pay big bucks.

I think "lack of ESD awareness " is on the rise malheuresement.

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