Author Topic: Ippon UPS: questionable snubber  (Read 4613 times)

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Offline Alex WolfTopic starter

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Ippon UPS: questionable snubber
« on: October 24, 2023, 07:24:46 am »
Hi there! 👋🏻

I was servicing one of my old UPSs (battery replacement), made a visual inspection of its board and noticed a strange snubber (schematic below): diodes D28, D29, capacitor C24, resistor R83.

1909689-0

The inverter is built according to the standard push-pull topology (sine wave approximation using square wave duty cycle with dead time). According to my analysis (picture below), the snubber does nothing useful, it just wastes energy. When the MOSFETs are turned on, the potential of the active half of the invertor winding arises on the inactive half of the winding in the indicated polarity, according to the phasing of the winding. This potential simply charges capacitor C24 to double the battery voltage (confirmed by measurement) and burns energy across resistor R83. When the MOSFETs are turned off, the back EMF is also applied to the mentioned capacitor and resistor. If we imagine a circuit without a snubber and add a capacitor in parallel to the battery (there is a place for it on the board, but it was omitted), then the back EMF will flow back into the battery through the MOSFETs body diodes.

1909695-1

Please correct me if I'm wrong. Am I missing something?
 

Offline fourtytwo42

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Re: Ippon UPS: questionable snubber
« Reply #1 on: October 24, 2023, 08:07:30 am »
I assume the transformer is Iron rather than ferrite and the switching speed very low perhaps even the grid frequency as the FET driver is very poor!
Having said all that the purpose of the snubber is to absorb the leakage energy from the transformer that would otherwise cause the positive going leg of the primary to far exceed the theoretical double supply voltage and destroy the mosfet. There are many way's to absorb this energy and almost all of them waste power, it is completely normal and unavoidable.
 
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Offline jonpaul

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Re: Ippon UPS: questionable snubber
« Reply #2 on: October 24, 2023, 08:11:56 am »
Inverter transformer  (any type, ferrite or iron) has leakage inductance.

The stored energy per cycle is 1/2 L * I exp 2

On each cycle,   stored inductive energy must be transferred elsewhere  or dissipated.

Both dissipative and non dissipative snubbers exist.

Without the snubber, high voltage spikes will stress the other components especially the switch transistors.

Jon
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Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #3 on: October 24, 2023, 06:28:53 pm »
Sorry guys, seems my question was formulated unclearly. I meant: in this particular case, can the snubber be redundant (unnecessary) if the back EMF energy flows back into the battery through the MOSFET body diode and the second half of the inverter winding (which was inactive in this cycle and has reverse phasing to the active half)? Like this:

1910121-0

But apparently the answer is no because of the stray inductance and imperfect coupling even in the case of a center-tapped winding, since in fact it is still two windings practically. Shame on me for missing the obvious.


In any case, this snubber doesn't work as intended anyway. Here are the waveforms of the MOSFETs Vds (BW limit 20MHz, probe x1, acquisition peak detect):



It is clear that the voltage spike exceeds 60V and the absolute maximum voltage rating of the MOSFET (CEP50N06 on this board). Fortunately, the spike is very narrow and doesn't have enough energy to destroy the switch transistors. I can assume that the problem is that the ESR of the electrolytic capacitor C24 (100uF 50V) is too high. The very first original design (which was ripped off) used a 470nF 1kV ceramic capacitor. There is also probably a problem with the board layout: the track between the snubber diodes and the capacitor is relatively long.

1910139-3

And here are the waveforms of the MOSFET Vds without the snubber (D28-D29 leads are lifted):



I'm going to replace the snubber capacitor with a 1uF 100V ceramic one and see how it performs.
 

Offline fourtytwo42

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Re: Ippon UPS: questionable snubber
« Reply #4 on: October 24, 2023, 07:40:10 pm »
Beware removing the snubbers!!

You are relying upon the avalanche characteristics of the mosfets to dissipate the leakage energy and although they are avalanche rated devices you do not know how much energy your transformer is throwing at them (relative to the mosfets specification).

The snubber circuit has been designed with  a large capacitor so I assume there is considerably energy available, if you dramatically reduce the amount of capacitance you may again destroy the mosfets. I see your comment about it possibly  being a rip-off and the capacitor value being changed BUT maybe they had to because they also changed the transformer for the worse and kept blowing up mosfets so in desperation they stuck that huge electrolytic in there!!

Using faster diodes and a film capacitor in parallel with the electrolytic would help damp the leading edge but this is probably unnecessary  with these particular mosfets.

One other point getting accurate scope shots is hard with high slew rate signals, I have had problems with poor probe grounding.

TBH is it worth trying to save a little energy at the cost of replacement mosfets and unknown reliability ?
« Last Edit: October 24, 2023, 07:53:00 pm by fourtytwo42 »
 
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Offline jonpaul

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Re: Ippon UPS: questionable snubber
« Reply #5 on: October 24, 2023, 07:43:20 pm »
MosFET avalanche is NOT specified nor intended for inductive leakage  energy dissipation.

The energy to dissipate per cycle is proportional to the leakage L and current peak, squared.

No snubbers>>blown MOSFETs


Jon
« Last Edit: October 25, 2023, 06:52:06 am by jonpaul »
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Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #6 on: October 25, 2023, 05:59:43 am »
Beware removing the snubbers!!

You are relying upon the avalanche characteristics of the mosfets to dissipate the leakage energy and although they are avalanche rated devices you do not know how much energy your transformer is throwing at them (relative to the mosfets specification).

Thank you for caring about the transistors 😁, but I relied on measurements and waveforms. Actually, that leading edge spike is the only problem, because the later ringing doesn't exceed the Vds breakdown threshold, which must be exceeded to turn a transistor in the avalanche mode. I saw the typical slow (and poorly designed) snubber waveform, which was there all the time since manufacturing and the transistors survived, the risk was minimized. Then I confirmed this assumption by cutting off the snubber circuit, and it was confirmed: the snubber does nothing useful at that load and inverter winding current (about 1A), the amount of avalanche energy remains the same (that spike above 60V, which is about 100ns wide and up to 10V tall). I didn't remove the snubber randomly and brainlessly just for fun, and I was ready for replacing the switch transistors in case of failure. And I assure you that there is nothing wrong with my acquiring of those waveforms: I used a short ground spring as the probe grounding and got the signal directly from the transistor’s drain and source leads.

Quote
The snubber circuit has been designed with  a large capacitor so I assume there is considerably energy available, if you dramatically reduce the amount of capacitance you may again destroy the mosfets. I see your comment about it possibly  being a rip-off and the capacitor value being changed BUT maybe they had to because they also changed the transformer for the worse and kept blowing up mosfets so in desperation they stuck that huge electrolytic in there!!

And how would you justify someone who omitted fuses that break the battery power supply circuit (about 200A peak unfused source)? Oh wait, I know: switch transistors are also pretty good fuses when the current is that high. 😁 Yes, I know, it's hard to judge comprehensively because I narrowed the description to the problem-related info only, but on the other hand, I didn't ask questions which is related to that background info. So yeah, it's a 120% rip-off with a bunch of issues hiding behind the scenes.

Quote
TBH is it worth trying to save a little energy at the cost of replacement mosfets and unknown reliability ?

I'm going to test it under full rated current, the cost and risk are zero. Energy efficiency is always worth the effort, but in this case I'm more concerned about the needles at the load output.
 

Offline Circlotron

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Re: Ippon UPS: questionable snubber
« Reply #7 on: October 25, 2023, 07:06:27 am »
1N4007 is a pretty slow diode. I'd put a pair of fast diodes or even a pair of schottkys there instead. That might help tame that spike.
 
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Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #8 on: October 25, 2023, 08:48:12 am »
1N4007 is a pretty slow diode. I'd put a pair of fast diodes or even a pair of schottkys there instead. That might help tame that spike.

Yes, I thought about this too, but in this case it won't help much, since the difference between a fast and a slow diode is mainly in the reverse recovery time, while in the forward direction they all are almost lightning fast. I bet that the main reason of that big leading edge spike (in about 2MHz ringing) is too large value of ESR and ESL of the electrolytic cap and high inductance of the relatively long trace to it. But this will slightly increase energy efficiency, so I replaced them with FR104s just in case. A dual 100V Schottky with a common cathode in a TO-220 package would also be nice there, but the PCB footprint is not suitable at all unfortunately.
 

Offline mtwieg

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Re: Ippon UPS: questionable snubber
« Reply #9 on: October 25, 2023, 11:37:11 am »
ninja edit: looks like you already addressed most of this in your first post, I'll just leave this here.

That's a pretty common type of snubber circuit. Yes, it will dissipate some extra power, but that's generally preferable to reducing the lifespan of the MOSFET.

It's odd that apparently it doesn't reduce the peak voltage stress on the FET, but does somehow dampen the ringdown after the peak voltage. It could be that the ESR of the snubber cap is too high to be a good path for the turn-off currents. The snubber performance will also depend greatly on the inductance in the path of the snubber itself. Hard to judge that without seeing the layout (edit: I can't load your photo, can only see the thumbnail).

Replacing the 1N4007 with a good schottky isn't likely to help much, since the transients are not very fast. Probably wouldn't hurt either though.

If you want to get a better sense for how much current the snubber is diverting, then you want to sense the high frequency current in the capacitor. Adding a small current sense resistor in series will allow this, and perhaps the whole circuit is isolated so you can clip your scope GND to Bat-V. Or connect the cap to ground instead of Bat-V (assuming its voltage rating allows for this), allowing you to probe the sense resistor while clipping the probe to circuit GND.
« Last Edit: October 25, 2023, 01:20:13 pm by mtwieg »
 
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Offline jonpaul

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Re: Ippon UPS: questionable snubber
« Reply #10 on: October 25, 2023, 12:05:13 pm »
First post scope shots DO NOT SHOW TIME SCALE (time/div)

Need to get the transient ring freq. perhaos a probe technique artifact.

Photo of the board with probes installed during scope shots?

Detail your probe/scope technique?

Measure peak I and Llkg of transformer.

Research regenerative (non-dissipative) snubbers.

See the very clever patents of M. VINCERELLI on a non diss snubber for FWD converters, the basis of Vicor power supplies.

Jon
« Last Edit: October 25, 2023, 12:19:51 pm by jonpaul »
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Offline mtwieg

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Re: Ippon UPS: questionable snubber
« Reply #11 on: October 25, 2023, 01:24:24 pm »
First post scope shots DO NOT SHOW TIME SCALE (time/div)

Need to get the transient ring freq. perhaos a probe technique artifact.

Photo of the board with probes installed during scope shots?

Detail your probe/scope technique?
Looks like the timescales are 5ms/div and 500ns/div, respectively. Ringing frequency is 3-4MHz.

Sounds like probing technique isn't an issue.

Might be worth trying to put a snubber cap directly from the primary center tap to GND, I bet that will clean up the Vds waveforms a bit (mainly the parts where both FETs are off).
 
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Re: Ippon UPS: questionable snubber
« Reply #12 on: October 25, 2023, 02:42:35 pm »
MosFET avalanche is NOT specified nor intended for inductive leakage  energy dissipation.

The energy to dissipate per cycle is proportional to the leakage L and current peak, squared.

No snubbers>>blown MOSFETs

Not unequivocally.  But I would certainly never suggest to rely on it.

In this case, it's probably a bad idea:
https://datasheetspdf.com/pdf-file/580997/CET/CEP50N06/1
Datasheet gives single avalanche rating, but not repetitive.  Now, maybe they just didn't care to test it for reps, but also possible is it accumulates damage.

It's most likely a common mid-generations trench type; the avalanche failure mechanism in these, AFAIK, is the "hot" electrons skating along the narrow web that is the channel in avalanche; inevitably some shoot out sideways, lodging in the gate oxide, inducing trapping defects, and eventual failure.  This is measurable by a shift in Vgs(th), though it's apparently quite a subtle change despite what it sounds like, and you don't know how far it can move before destruction occurs.

Contrast with HEXFETs and such (older generations), where the gate oxide is on the top surface and the channel lies in a depletion region beneath; avalanche occurs under the source contacts/diffusions, beside the channel, which is more or less dead wasted space in conduction, hence the low area performance of HEXFETs, but also the reason for their famous avalanche robustness -- including repetitive, usually!

Compare IRFZ46N for example, a similar sized HEXFET: https://www.infineon.com/dgdl/irfz46npbf.pdf?fileId=5546d462533600a40153563b734b2220




OP: what you're missing is two things:

1. Your equivalent diagrams omit the RC, for some reason, showing diodes shorting out the winding, which obviously isn't the case.  I suppose one could draw such an equivalent for maybe the first half-cycle, before the capacitor is charged to peak voltage, but at such low frequencies, and no current limiting to speak of, it'll charge very quickly indeed.  Just for purposes of illustrating the current flow directions, and switching phases, yes, that will be correct, but the magnitude of diode currents will be wildly unrealistic (and transformer voltages for that matter).

2. No transformer is perfect.  The key here is leakage inductance, which manifests as a lone, uncoupled (because it's leaking out from between the windings!) inductance in series with each terminal.  Since it doesn't couple, it doesn't contribute to transformer action, it doesn't contribute to magnetizing current/inductance, it bears no relation to the intended current flows, and acts as parasitic waste in the circuit -- it must be charged to peak output current every cycle, then discharged at turn-off.  We can therefore model it as a flyback circuit, and a simple RCD clamp snubber will do the job.

Length of the snubber trace does look quite ponderous, and a capacitor installed near the diodes would be preferable (the adjacent node is GND I believe, which is an AC supernode where the capacitor can also connect), but keep in mind the transistor turn-off isn't exactly rapid, the gate drive is quite weak here.  This is reflected in the relatively long (>500ns) turn-off, which likely gives plenty of time for current to shift into that longer path.  The resulting equivalent circuit will be some stray inductance in series with the diodes' common cathode path, maybe 30-50nH, and therefore the two inductances (the leakage/flyback and snubber stray) act in series as an impedance divider, leaving some peak voltage at the MOSFETs, but I'm assuming leakage is dominant here (100s nH? ~uH?) so the peak will be small.

BTW, 1x probes are useless for switching circuits, the bandwidth is about 7MHz typically; check your probe datasheet.  Please use 10x, and check compensation against the scope cal point to ensure a nice flat square wave before taking measurements.  BW limit can then be raised from 20MHz as well.  It's likely that actual avalanche was in fact going on here, and just not measured due to the lack of bandwidth.  Which means you've unwittingly/unknowingly put wear on the transistors, and risked their destruction in the process.

Anyway, a film capacitor is indeed ideal here.  I'm not sure where you'd find a "470nF 1kV ceramic", but I'm assuming that's just a typo, and some ~uF MLCC will be fine as well, but do beware C reduction under bias.

The minimum value can be calculated from LL, peak turn-off current, and desired peak voltage change, since the flyback circuit forms a resonant tank with the inductor and capacitor (it goes through < 1/4 of a wave, due to initial voltage plus the diode terminating the ringing wave partway through, but it is in fact going through a section of an LC ringdown waveform in the process).  Taking ballpark figures of 1uH, 50A and 10V, sqrt(L/C) = (10V/50A) needs C > 25uF.  I would suggest replacing the original with a low-ESR electrolytic, or polymer even if you like, and placing the MLCC by the diodes.  This addresses both the stray inductance, some of the electrolytic's ESR (but not much considering the large expected value of C), and the apparently dry (or not-well-performing anyway) original capacitor.

...Oh, hah, 1N4007 huh?  Those will dissipate quite some power in recovery as well, which likely didn't help the electrolytic in there.  I would rather a medium-fast recovery type like FR102.  Or even a 3A diode, if it'll fit.

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Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #13 on: October 26, 2023, 11:01:59 am »
Brief update (I'll answer everyone a little later).

I replaced the diodes D28 and D29 with fast FR104s, left in place the snubber elcap C24 (100uF 50V), bypassed it with an SMD cercap 1uF 100V, returned the omitted capacitor C14 (between BAT-V and PGND) using an elcap 470uF 63V, bypassed it with an SMD cercap 1uF 100V. Effectively this creates a low impedance loop for that 2-4MHz ringing frequency between MOSFETs' drain and source through the diodes and capacitors chain (snubber>BAT-V>PGND). And it partially worked, here are the waveforms of Q20 Vds under the same test conditions (Irms=1A) as above (except the probe: now it's x10 with BW 200MHz (it's compensated - doublechecked), no BW limit on CH1):



But still the snubber reaction is delayed for 100-200ns, which causes the same huge spike up to MOSFETs Vds max under load conditions. Here are the waveforms of Q20 and Q23 Vds (both inverter shoulders INV-1 and INV-2) under center-tap Irms=10A:



And here are the waveforms of Q20 Vds under Irms=15A (after which I had to stop the test, as I ran into Vds max with that spike):



Taking into account the fact that the rated RMS current of the inverter winding is 50A, I'm wondering how it worked before so long time. 🤔
« Last Edit: October 26, 2023, 12:53:09 pm by Alex Wolf »
 

Offline mtwieg

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Re: Ippon UPS: questionable snubber
« Reply #14 on: October 26, 2023, 12:02:02 pm »
What do you see if you probe the voltage on C24? It should be hovering just below the peak Vds. If so then reducing R83 should also reduce the peak Vds.
 

Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #15 on: October 26, 2023, 12:23:24 pm »
That's a pretty common type of snubber circuit. Yes, it will dissipate some extra power, but that's generally preferable to reducing the lifespan of the MOSFET.

There was a slight misunderstanding. I don't mind that it dissipates some power as a snubber. I just don't like that in this particular case it dissipates much more as a rectifier (but not that much, see below).

Quote
It could be that the ESR of the snubber cap is too high to be a good path for the turn-off currents.

Exactly what I thought, and this was confirmed (see the post above), but it was only part of the problem.

Quote
The snubber performance will also depend greatly on the inductance in the path of the snubber itself. Hard to judge that without seeing the layout (edit: I can't load your photo, can only see the thumbnail).

Strange, I used the forum engine (so that the images won't disappear from the topic over time, as it happens with third party image hosting). It should have worked fine, like all other images uploaded to the topic. Nevertheless, here are the full-size better photos with markups:

1911642-0

Full size link (tested)

1911648-1

Full size link (tested)

As you can see, both the snubber and power ground traces to the damper capacitors are relatively long, about 9cm (3.5inch).

Quote
If you want to get a better sense for how much current the snubber is diverting, then you want to sense the high frequency current in the capacitor. Adding a small current sense resistor in series will allow this, and perhaps the whole circuit is isolated so you can clip your scope GND to Bat-V.

I'm sorry, but I haven't gone deep enough down the rabbit hole yet to cut traces and bridge it with a resistor. 😁 Maybe later.
I use a scopemeter, its ground is floating, so can be clipped anywhere. To get an idea of the amount of energy that the snubber resistor dissipates, I got its waveforms under 1 and 10 amps RMS (probe GND is on BAT-V, acquisition mode is sample, zoomed part is the snubber action):

Irms(ct)=1A



Irms(ct)=10A




This is what I was talking about above: the bulk of the energy that the snubber resistor dissipates comes from operating as a rectifier, compared to the small overhead of operating as a snubber. But after recalculating it with exact numbers (10.7Vrms/296.8R), it turned out much less than I expected looking at the five-watt resistor: just less than 400mW, and it's barely warm.

Quote
Or connect the cap to ground instead of Bat-V (assuming its voltage rating allows for this), allowing you to probe the sense resistor while clipping the probe to circuit GND.

Funny, but this made me think about the next step in refining the snubber: shorten the long loop by shunting with another ceramic capacitor between the cathodes of the D28-D29 diodes and B- terminal. They're close enough for 1206 SMD cercap. I'll write how it went later. Thanks!

What do you see if you probe the voltage on C24? It should be hovering just below the peak Vds. If so then reducing R83 should also reduce the peak Vds.

It is rightly said that smart people have similar thoughts. 😁 When you post this reply, I was just replying all this above to your previous reply, having previously taken the waveforms of the R83. Seems that the leading edge spike doesn't reach the capacitor.
« Last Edit: October 26, 2023, 12:27:42 pm by Alex Wolf »
 

Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #16 on: October 26, 2023, 03:39:59 pm »
OP: what you're missing is two things:

First of all: wow! I must admit that this is a complex and comprehensive answer, I appreciate it, respect. 👍🏻

Quote
1. Your equivalent diagrams omit the RC, for some reason, showing diodes shorting out the winding, which obviously isn't the case.  I suppose one could draw such an equivalent for maybe the first half-cycle, before the capacitor is charged to peak voltage, but at such low frequencies, and no current limiting to speak of, it'll charge very quickly indeed.  Just for purposes of illustrating the current flow directions, and switching phases, yes, that will be correct, but the magnitude of diode currents will be wildly unrealistic (and transformer voltages for that matter).

Yes, these equivalent circuits are a very crude approximation. As you noticed in the second part of this remark, I was only trying to show two possible paths of the back EMF current when I analyzed the operation of the snubber in the presence of MOSFETs body diodes, questioning the need for two of them. But of course you are right, the RС constant must be taken into account in the general case. I should have noted this so as not to mislead anyone or look like a fool.

Quote
2. No transformer is perfect.  The key here is leakage inductance, which manifests as a lone, uncoupled (because it's leaking out from between the windings!) inductance in series with each terminal.  Since it doesn't couple, it doesn't contribute to transformer action, it doesn't contribute to magnetizing current/inductance, it bears no relation to the intended current flows, and acts as parasitic waste in the circuit -- it must be charged to peak output current every cycle, then discharged at turn-off.  We can therefore model it as a flyback circuit, and a simple RCD clamp snubber will do the job.

For some strange reason, my brain decided to treat the center-tapped winding as one solid winding, rather than two separate and imperfect ones. I don't even know how this happened, but I must admit that it was really stupid. I already realized my mistake and wrote about it in my second post, but thank you for a clearer and more comprehensive explanation. By the way, later I treated this parasitic leakage inductance as an independent inductor in series with the transformer.

Quote
Length of the snubber trace does look quite ponderous, and a capacitor installed near the diodes would be preferable (the adjacent node is GND I believe, which is an AC supernode where the capacitor can also connect), but keep in mind the transistor turn-off isn't exactly rapid, the gate drive is quite weak here.  This is reflected in the relatively long (>500ns) turn-off, which likely gives plenty of time for current to shift into that longer path.  The resulting equivalent circuit will be some stray inductance in series with the diodes' common cathode path, maybe 30-50nH, and therefore the two inductances (the leakage/flyback and snubber stray) act in series as an impedance divider, leaving some peak voltage at the MOSFETs, but I'm assuming leakage is dominant here (100s nH? ~uH?) so the peak will be small.

I think that the engineer who developed the original design deliberately slowed down the switching of the transistors, taking into account the highly imperfect iron-core transformer for high frequency / short rise time. The same thought occurred to me, to slow them down even more (if other options will not work), looking at its transients under a rather small current relative to its rating. I'm sorry, I haven't measured it accurately yet to confirm or refute your assumptions about the values, I'm still trying to take a shortcut to fix it, instead of completely redoing the calculations for this part of the circuit. And I will try to literally shortcut the path through the capacitor between the cathodes of the diodes and the power ground polygon. By the way, the transformer dissipates about 10W of energy at idle, so this is definitely not the best example, very far from perfect.

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BTW, 1x probes are useless for switching circuits, the bandwidth is about 7MHz typically; check your probe datasheet.  Please use 10x, and check compensation against the scope cal point to ensure a nice flat square wave before taking measurements.  BW limit can then be raised from 20MHz as well.  It's likely that actual avalanche was in fact going on here, and just not measured due to the lack of bandwidth.  Which means you've unwittingly/unknowingly put wear on the transistors, and risked their destruction in the process.

Can't wait to see the destruction of my transistor captured on a scope? 😁 Sure, no problem. I used the x1 divider and bandwidth limit deliberately, after making sure that there were no high frequencies with high energies in the measured circuit, in order to reduce the level of high-frequency low-energy noise. This is just an SMPS of the very low mains frequency with the very slow transistor switching (as you noted above, which I also noticed): there is simply nowhere for high-frequency bursts to come from (except the avalanche breakdown). I'm aware of the rise time and bandwidth limitations in x1 divider mode, in this case it's 6(10)MHz and 35ns, should do the job. But it's a good call to capture all the details you can capture when you're looking for something you don't completely know what, so from this moment on in this topic all waveforms were taken with the probe in x10 and without the bandwidth limit on the channel. And congratulations, you have successfully planted a seed of doubt in me, so I ran to recheck the probe compensation: everything is fine, the tops are as flat as the Earth. JK 😁

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I'm not sure where you'd find a "470nF 1kV ceramic", but I'm assuming that's just a typo

Yes, it would be a very difficult task, no doubt.

Quote
The minimum value can be calculated from LL, peak turn-off current, and desired peak voltage change, since the flyback circuit forms a resonant tank with the inductor and capacitor (it goes through < 1/4 of a wave, due to initial voltage plus the diode terminating the ringing wave partway through, but it is in fact going through a section of an LC ringdown waveform in the process).  Taking ballpark figures of 1uH, 50A and 10V, sqrt(L/C) = (10V/50A) needs C > 25uF.  I would suggest replacing the original with a low-ESR electrolytic, or polymer even if you like, and placing the MLCC by the diodes.  This addresses both the stray inductance, some of the electrolytic's ESR (but not much considering the large expected value of C), and the apparently dry (or not-well-performing anyway) original capacitor.

Thanks for this detailed tutorial, I will definitely put it to good use. BTW, C24's ESR is roughly 400mR and it's not dry, but it was soldered on long leads made of ferromagnetic material (definitely not copper).
« Last Edit: October 26, 2023, 03:45:13 pm by Alex Wolf »
 

Online T3sl4co1l

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Re: Ippon UPS: questionable snubber
« Reply #17 on: October 26, 2023, 06:12:18 pm »
Ah, cheers.  Seems I interpreted the couple... omissions? mistakes? simplifications?, as overly beginner-level, but that's not so much the case as it turns out. :-+

Downside about the waveforms is the obvious noisiness, upside is they're very easy to read: currents switch from one path to the next, gated by diode(s) and the developed voltage:



L_Q being for lack of a better symbol, the inductance of the transistor Qn.  Leading edge is due to L_Q + Lsnub.  Eventually, load current (shown here as a big iron-core inductor, partly magnetizing inductance, partly leakage; what's going on at the far end of the CT winding isn't too important for these purposes) decays to such a point that the free ringdown voltage of the transformer is below the snubber voltage, and the diode turns off.  And being that it's very lossy, it actually just slumps down I suppose along an L/R time constant, rather than ringing at all.  But if it were a ferrite core transformer, you'd see much the same ringing as from the MOSFET-to-snubber commutation (just at a much slower rate, much higher impedance), and for much the same reason. :)

If you want to slow things down, you might consider some dV/dt rate control.  Note that gate drive is quite limited, ~4mA say, and we can use Miller effect to enforce the voltage rate.  Let's see, say we want 30V in 500ns, at 4mA that's C = I / (dV/dt) = (4mA)*(0.5us) / (30V) = 0.067nF.  We don't want to put a hard capacitor between D and G, but some series resistance should be present, say 470 or so.

Note that CEP50N06's Crss is already small, like ~100pF at high Vds, so it's no accident it rises quickly despite the slow gate drive.  If it is actually 100, presumably tripling that by adding say 220pF would do the job as well (the 20-50V range is covered in just 100, 200ns, thereabouts), so again we have something in the mid pF's we could try.

ESR should probably be reduced, and notice that small bypasses don't do much, or make things a little worse even (more complex waveform, maybe more EMI; not necessarily in terms of peak voltage specifically, which should still trend lower), because again, the relevant capacitance is 10s of uF.  A few uF hardly does anything.  Say peak current is 50A: dumping that into 400mΩ throws away 20V already, and the snubber starting from 24V (since it skates across the tops of alternate square peaks) basically throws away all your Vds overhead.  So, aluminum polymer is pretty much the perfect choice for this kind of application.

Tim
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Offline mtwieg

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Re: Ippon UPS: questionable snubber
« Reply #18 on: October 28, 2023, 05:54:21 pm »
So to summarize what I see in the waveforms so far,
1. The peak Vds is around 60V
2. The peak voltage across the snubber is 12-14V
Assuming that BAT-V is around 12V (with no significant spikes) where the snubber connects to it, that means that the voltage between the FET drain and the snubber peaks at 30V, as opposed to the <1V we'd expect from the diode's Vf. Obviously we should expect to see more than a volt, but 30V implies that something else is amiss. Could you try probing the voltage at the cathode of the snubber diode(s), with the scope GND connected to the same place as when you measured Vds?

According to your schematic, the FETs are turned off with a series resistance of 1.2k on each gate. That's not actually true, right? CEP50N06 datasheet says Cgd is 50pF and the gate plateau voltage is 3V, so with 1.2K on the gate the max dV/dt on the drain should be just 50V/us. But from your waveforms it looks closer to 200V/us  :-\
 
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Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #19 on: December 10, 2023, 05:52:49 pm »
I apologize for taking so long to update the topic. At first, I didn't have time to play around with this UPS, then I didn't have time to put in order all the heavily abbreviated notes and files about it. Anyway, if anyone is still interested and for completeness of the topic, better late than never, here’s what came out.

All assumptions about the reasons for that leading edge spike were correct. Literally every one, I checked them all step by step out of practical interest. The reasons were the capacitor with too high ESR, bad diodes with too high instantaneous Vf, and the trace that was too long. I ended up squeezing in SR380 Schottky diodes, adding a Panasonic 47uF 50V low impedance long life elcap with a Samsung 4.7uF 50V cercap bypass as close to the switch transistors as possible. It looked something like this (in the photo are previous 1N5822 test diodes, later they were replaced with SR380):

1949853-0

I also replaced the switch transistors with STP55NF06 and their gate resistors with 100R. And here is what it looked like on the scope, before with FR104 and after with SR380, CH1 D28 Vk vs CH2 D28 Va to PGND (note the different V/div):



Same under full load:



And this is what the inverter output voltage looked like before and after the modification:



Thank you all for your helpful thoughts, they really saved me significant amount of time than if I had dealt with this case alone.  :-+


I also replaced some capacitors on the power rails and sense lines to reduce ripple and improve stability, tweaked the battery charge and discharge values to optimal, modified the indication panel, etc., but I doubt that this will be of interest to anyone. 🙂
 
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Offline Alex WolfTopic starter

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Re: Ippon UPS: questionable snubber
« Reply #20 on: December 10, 2023, 06:16:27 pm »
Downside about the waveforms is the obvious noisiness, upside is they're very easy to read: currents switch from one path to the next, gated by diode(s) and the developed voltage...

Not for the sake of argument, but for the sake of completeness of the topic, and simply because I can better see the live circuit in person, this is how I would present all the components that are significant for the waveform contribution (the green ones were added, the yellow ones were changed):

1949883-0

Yep, it has active clamp during dead time with roughly 5us delay.

I simply have nothing to add to the rest, perfectly described and thank you!  :-+

Could you try probing the voltage at the cathode of the snubber diode(s), with the scope GND connected to the same place as when you measured Vds?

And that was a great idea that saved a lot of time, thanks!  :-+ You can see the waveforms above.

Quote
According to your schematic, the FETs are turned off with a series resistance of 1.2k on each gate. That's not actually true, right? CEP50N06 datasheet says Cgd is 50pF and the gate plateau voltage is 3V, so with 1.2K on the gate the max dV/dt on the drain should be just 50V/us. But from your waveforms it looks closer to 200V/us  :-\

Accurately noted! The gate resistors were 220R (then I changed them to 100R, since the STP55NF06 is a little slower than CEP50N06).
« Last Edit: December 10, 2023, 06:20:20 pm by Alex Wolf »
 


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