Avoiding reverse recovery problems in LLC converters

[Faringdon]

Hi,
Is the attached an excellent  way of avoiding damage from reverse recovery in offline LLC converters?
A Low Vf,  Standard, Si Diode is simply placed in series with the Si FET, so as to stop its intrinsic diode from ever conducting.......another diode (SiC)  then conducts the "freewheel", backflow current as shown.
Problem solved?......even go into the capacitive region and no  damage from reverse recovery will  ever occur?

(LTspice and jpeg attached, should you wish)

BTW, adding the said diodes is unlikely to impact efficiency...(even if it did , it would be only 0.5% max).....but  actualy it wont impact efficiency at all.....because using these diodes means you can use the lowest rds(on) FET that you can find.......this is not usually allowed with LLC converters, as its usually wanted to use a fet with high enough rds(on) such that  the current flow through it puts enough reverse voltage across the intrinsic diode to sweep out its minority carriers...............but when you use the diodes, this no longer applies.

[Faringdon]

...continuing, if i may...
The attached LTspice simulation shows how to totally solve reverse recovery problems in the LLC converter! It shows an LLC with a series diode and parallel SiC diode…..and as a comparison  an LLC with just  normal  Si FETs in the leg.
The switching frequency is taken down into the capacitive region ……the “series diode LLC” suffers absolutely zero diode reverse recovery!!!.......you  can see that there are high current spikes , but doing the calculation, you can see that these spikes correspond  only to what you expect to see due to the sudden discharge of the FET stray capacitance….not reverse recovery.
Whereas the LLC with no series diode suffers from quite utterly horrendous reverse recovery current spiking…FET killers !!!...how many of those reverse recovery spikes does it take to kill a FET?....probably  just one!.........and even if the FET doesn’t die…it will be weakened such that it will soon die.
Maybe  it is thought we can simply avoid the capacitive region by setting a minimum switching frequency……but this only works if your load never deviates from maximum….eg overload or short or startup, or restart, or return from temporary brownout etc etc…..when  that happens the LLC resonant frequencies change such that  our “minimum frequency” is no longer well set…..and we stray into the capacitive region anyway……..i wonder does anyone yet believe that they can detect  the first LLC hard switch of a  series of them?…..ie, detect it before it actually it happens…so you can avoid switching on at all…..i very much doubt anyone has done this….though there is an Infineon App note where work toward that has been done….maybe they succeeded?
But anyway…you can eradicate the problem by using the series standard diode as shown here (nice low Vf) and parallel SiC diode. And as a bonus, you get to pick the lowest rds(on) FET that you like!!!...no more worrying that the rdson isn’t going to be big enough to raise vds sufficiently during ON time so as to sweep out minority carriers in the intrinsic diode……the intrinsic diode is not going to conduct because your series diode has blocked it!
You now have an LLC converter, that, as long as you have current sense transformer/comparator primary side, is just as tame as a  little DCDC buck converter!
And you loose no efficiency…because you can now choose the lowest rdson FET.

[David Hess]

A pair of diodes like you show to isolate the body diode is the usual recommendation.  Some power MOSFETs are specifically designed to have lower reverse recovery loss of their body diode.

[Faringdon]

A pair of diodes like you show to isolate the body diode is the usual recommendation

Thanks, i must confess i have been looking for articles on this, but found none, which surprises me.
Also, is the actual reverse recovery of the added-in series diode an issue at all?.....i presume it still needs to be reverse recovered fairly  promptly?.

Also , as the attached LTspice shows, the voltage across the series diode can be greatly reduced by putting 100pF to 1nF across it...though i suppose its part of a capacitive divider with the fet CDS's....also, i am reluctant to put a cap across it, as it provides a bit of a conduction path for the dreaded intrinsic diode. What would, may  i ask, you yourself do? And how low in voltage would you rate this diode to?....i reckon its 500Vmax...but any less is a bonus...being a nice Standard diode its got low Vf , even at 500v

[Faringdon]

Thanks for all replies...
It seems odd that no Application Note, or article, anywhere on the web, discusses the herewith_discussed use of a series diode (plus sic antiparallel diode) with a LLC converter...

https://www.st.com/resource/en/application_note/an2644-an-introduction-to-llc-resonant-halfbridge-converter-stmicroelectronics.pdf
https://www.infineon.com/dgdl/Application_Note_Resonant+LLC+Converter+Operation+and+Design_Infineon.pdf?fileId=db3a30433a047ba0013a4a60e3be64a1
https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Application%20Note/lang/en/sku/HR1000AGS-Z/document_id/5926
https://www.onsemi.com/pub/collateral/and90061-d.pdf
https://vtechworks.lib.vt.edu/bitstream/handle/10919/28982/Ch4.pdf
https://www.power.com/sites/default/files/documents/an55.pdf
https://ww1.microchip.com/downloads/aemDocuments/documents/OTH/ApplicationNotes/ApplicationNotes/LLC_Appnotes.pdf
https://www.monolithicpower.com/en/support/videos/design-a-600w-llc-converter-for-a-pc-power-supply.html
https://psim.powersimtech.com/hubfs/PDF%20Tutorials/App%20Notes/Design%20of%20Resonant%20LLC%20Converter%20for%203.3-kW%20On-Board%20EV%20Charger%20(AN003).pdf

...Nobody mentions it......which makes you wonder how they are all avoiding severe reverse recovery?

The only mention of it is Infineon, in one App Note, where they claim to have software which can detect severe reverse recovery just before its about to happen....and then allows you to not switch the fets on, so that you can totally avoid it......that, realistically , is the only other way to avoid severe reverse recovery in the LLC  if you dont use the series (& antiparallel)  diodes.

Seems strange its not discussed anywhere though.......specially since one single  instance of severe reverse recovery can severely weaken or kill the LLC converter.
And it seems strange that Infineon aren't talking up their software detection of Reverse_recovery_imminent.....if they have really got software that does that...then it is surely the biggest revolution in SMPS since a long time....why so schtum?

[JohnG]

I will preface this by saying that the last LLC I designed was before they were called LLC converters, so keep that in mind.

However, I have been involved in power semiconductors for some years now, and seen quite a few LLC designs for telecom rectifiers and some lower power ones for consumer use. Most of these have an LLC for the 400V to xxV output stage, and none of them use this diode trick. Until recently, they all used superjunction MOSFETs, which have notoriously bad reverse recovery. All the ones I have seen have some relatively sophisticated custom control to handle all kinds of edge cases. It also seems like as much time is spent handling edge cases as the main use case, which should not be a surprise to anyone with experience building a commercial power converter for sale.

The diode trick you show has been around for a long time. If I recall correctly, it was first used for early power MOSFETs because hard shutoff of the body diode could sometimes latch up the FET like an SCR. But, it has some real problems. The capacitances of the series diode and FET should be such that you don't overvoltage the series diode, but you also want to avoid too much capacitance on the diode. The extra voltage drop of the series diode is extra conduction loss, and if you use a Schottky diode, you need to make darn sure you don't avalanche it. Plus, modern FETs are really fast, so if you start to throw in some realistic parasitic inductances, things don't look so nice anymore.

John

[Faringdon]

Thanks, yes, those are great points.  AYK, the series diode gives extra conduction loss.....though luckily it means you can now use  a really low rdson FET , whereas without it, you have to be wary of the fact that a low rdson fet may not  have enough conduction vdson to properly reverse recover the internal  fet diode.

Agree about the design for edge case......

AYK, the thing with LLC,  is that those edge cases involve anything that may bring about  the reverse recovery......so thats overload, short cct output....undervoltage input.....startup, re-start-up, heavy load transients, and some more. Also, since even one single instance of the reverse recovery in an LLC can kill or seriously weaken the converter,  the detection needs to detect the disaster before it happens, and then stop switching the fets so it doesnt happen..........to detect  this  (imminent_reverse_recovery) in that timescale is extremely challenging.......as discussed, infineon claims to have LLC circuitry and software that can do that ( i think they do?)...........but if it works, then it is truly amazing........without that software based proteciton, it needs the series diode to be sure of not getting  reverse recovery based destruction.

....AYK, its an old technique, but i believe needs re-introduction due to the   rising popularity of the "current sloshing" converters like the LLC....AYK, "current sloshers" slosh the primary current about so that the fet diode comes on just vefore the fet switchs on........others in the  same category, AYK, are Phase shift full bridge and  the "Half_bridge_with_big_leakage_inductance_but_no_output_inductor"...aswell as  one variety of the forward converter if the leakage L in the txfmr is big enough. (Active clamp forward).

AYK, the problem with "current sloshing", is that it can get "out of phase", and the diode can get sloshed on just as the opposite fet is turned ON....literally one single instance of this can kill or seriously weaken the converter....thats why its so difficult to avoid if you dont use the series diode.

I agree about the parasitic inductance getting increased when you add the series diode......we would try and switch the LLC fet on very slowly, and wish to get away with that due to the fact that its in ZVS.......but yes, i agree, the extra parastic inductance is certainly not welcome.

But yes, and its literally amazing that the App Notes  and semico's dont talk of this.......touting LLC controllers without mentioning it isn't a great idea...some of the LLC App Notes work through Ohms Law calcs with you......but then dont bother to tell you about the reverse recovery issue.

And if infineon really do have that avoid_reverse_recovery software....then the Nobel Prize wouldnt be enough for them!...or even a mention on BBC's  "click" program!!

[julian1]

The first thing I did with my limited low-power prototype after winding the transformer, is re-test the primary inductance (it changed slightly after adding the secondaries). Then re-calculate the tank resonant frequency, based on the LC (resonant inductor + transformer magnetizing inductance, and blocking cap).

Then put hard asserts in the code for PWM generation with a large margin of error, to avoid the capacitive region. So if tank was 30kHz, it was impossible to stray below 40kHz, and startup freq was set at an order of magnitude higher frequency (ie. 300kHz). Then hook up the scope, for first run, to confirm expected behavior, slowing reducing the frequency down, and observe primary voltage swing, and power levels.

I don't believe the resonant tank frequency changes (much) under varying load conditions. My understanding, is that any control loop would just avoid following output power demand, down into capacitive frequencies.

My experience is limited to hobbyist level/prototype/ demonstrative design - a basic low-power DC/DC prototype, so Caveat emptor .

[Faringdon]

Thanks, yes  great points.....in normal conditions, AYK,  you can set a minimum frequency and never go into the capacitive region....but its during the abnormal conditions as described above where things change and you can still end up in the capacitive region....even though a min freq was set.  The actual power stage  calculation is different in the abnormal conditions and   a frequency that was deffo out of the capacitive region, is no longer.

[Faringdon]

Would you agree, this method means the dead time of the LLC converter  needs reducing?...because the "Effective Cds capacitance" is now reduced...since there is a diode in series with the FETs Cds....so less "effective Cds".

[Faringdon]

but you also want to avoid too much capacitance on the diode.

Thanks,
the said diode (the lifesaving series diode), is in series with the FET, so its capacitance will be  in series with the FET capacitance, so i woudlnt think it will cause too much problem?