Hi,
Most SiC want reverse bias,
Thanks, i take it that you are referring to Bipolar gate drive here(?)....
The attached (LTspice and jpeg) has bipolar FET drive…but when you trace out the gate drive loop, you are going through more components…….through each of the split caps….and it looks like there will be significant gate drive path inductance…leading to the problems that bipolar drive was put there for in the first place. I think if the gate drive is very well damped, then bipolar drive looks OK….but not otherwise. I can see bipolar drive being good with IGBTs for drives, which have low switching frequency, and so it can be well damped.
The PNP turn off circuit, when put right next to the FET in question, does appear to be the best, low impedance way to guarantee the FET staying off. And of course, you can’t have “PNP turn off” AND “Bipolar FET drive” together.
Would you agree?
I think bipolar drive may be OK though, if you could have the bipolar driver and components done in SMD and right next the fet being driven, with very tight layout…..but on a big power board, you cant have SMD on the board, as you know, the SMD has to be on a daughter board…..so you’ve got to route off to that, and then you get more stray layout inductance.
I think Bipolar drive is greta in principle….but on a big power board, when you come to do it…..it doesn’t look better than a PNP turn off circuit.
I think the emergence of “Active miller clamp” on the modern gate drive IC’s is testimony to the fact that Bipolar gate drive has problems, and other ways need to be looked into……the “Active miller clamp” method , of course, is basically a PNP turn-off circuit.
Would you agree?