Electronics > Power & Renewable Energy

Boost converter: Where to best place CST?

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Do you agree the low side CST position is better since it means no overvoltage spiking to the FET?
Also, the leakage inductance of the CST provides some reduction in gate drive dv/dt and thus improves EMC?
PDF schems and LTspice sims of low-side and high-side CST positions attached

What is CST?  When you use acronyms you fend off many potential replies.


--- Quote from: bob91343 on June 13, 2021, 08:34:06 pm ---What is CST?  When you use acronyms you fend off many potential replies.

--- End quote ---

Based on schematic CST==Current Sense Transformer, which is a stupid acronym. I've only heard Current Transformers abbreviated "CT".

In any case, the high-side version is better electrically since there is no sense coil in the gate drive path, and no extra impedance.

As said, inductance on the source slows down the switching.

Also, for the same di/dt you get the same voltage spike due to leakage inductance. Except now its a negative voltage on the source instead of a positive voltage on the drain.

Any reduction of DS voltage stress is going to be due slower switching caused by the added source inductance. If this is an issue, you might as well just slow down the gate drive with a gate drive resistor, that's more adjustable.

Additionally, Treez/ocset, if you are going to keep creating alt accounts to get people to do your job for you consider changing your phrasing so its not immediately obvious  :-// 

Thanks, ..are there any other ways to get high bandwidth current sensing like this, other than using a sense resistor?
Eg, any really fast Hall type sensors.
As you know, its needed to depict the trapezoidal fet current very accurately (for current mode control) and without filtering it  too much.

Ive heard of people using a really low value sense resistor and then amplifying this with a really fast op-amp, have you heard of this?


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