CLC filter worse for ripple current

[Faringdon]

Hi,
Page 22 shows an CLC mains input filter....
AN-70
https://www.power.com/sites/default/files/documents/an-70_linkswitch-tn2_design_guilde.pdf

If the two electrolytic  caps just got paralleled, and the inductor was put in the AC section, then  there would be less overall ripple current stress to those two electrolytic capacitors. This is obvious, and i have a sim to proove it.
So why do they use a CLC filter?

[CosteC]

This filter not only reduces ripple to SMPS, it also prevents noise from exiting SMPS into mains. Hence its PI construction. I think.
Awful half-cycle rectification contraption...

[Phoenix]

Put a LISN in your simulation and look at the mains conducted noise.

[Faringdon]

Thanks, i can see the noise conducted by looking at the current, and its smooth without pi filter

[pardo-bsso]

Also keep in mind that several filter topologies in power supplies change their steady state behaviour drastically if the current through them goes to zero.

[Faringdon]

This filter not only reduces ripple to SMPS, it also prevents noise from exiting SMPS into mains. Hence its PI construction

Thanks, though as you know, we dont absolutely need PI construction for this. So why PI.?..why not preserve the input electrolytic  caps....we can put filter inductors in the AC section and prevent noise escaping the SMPS.