Electronics > Power/Renewable Energy/EV's

Interesting- SiC JFETs as the next-gen switching devices

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schmitt trigger:
This may be old news to some advanced folks here, but to me it was a revelation;

Looking for something unrelated, I stumbled into this white paper, which I believe will be of great interest to people interested in Power Electronics.
The WP’s name is a little misleading, as the real breakthrough IMHO, is the use of SiC JFETs as power switching devices. JFET devices are normally ON, so how do you use them for switching? With a cascode configuration, that is how.

Please comment. As I mentioned earlier, if these devices really deliver the performance gains and don’t have some weird failure mechanisms, they have the power (pun intended) to revolutionize the SMPS industry.
What do you think?

These parts have been available for at least some six-seven years from USCi/UnitedSiC, now owned by Quorvo. They are competing with plain SiC MOSFETs, from Wolfspeed, Infineon, Onsemi, ST, Rohm among others, also with a similar history of availability.

SiC power semiconductors really are as amazing as they seem, and a total game changer for high voltage power conversion. The first buck converter I made with SiC MOSFETs managed to do 16 kW with a pair of TO-247 devices with a die area of less than 7 mm^2 each. Efficiency was above 99 % at 800 V in, 450 V out and 10 kW power.

Price used to be an argument against SiC, but when working with DC bus voltages above 400 V and considering Rds_on losses at realistic junction temperatures, they are much cheaper than any silicon MOSFET technology I've seen. And considering the savings in magnetics due to being able to use higher switching frequencies with a given loss budget, it often comes out a lot cheaper from a systems perspective. A similar argument can be made regarding cooling system cost, SiC can operate with lower losses, higher junction temperatures and with less of a conduction loss penalty at high Tj.

I'm of the impression they're the older technology.  They were the first type to release, I think.  Not to say they're falling behind or anything; they've been asymmetrical* from the start (by necessity), and have incorporated SJ since then, I think.

*That is, max Vgd != Vgs.  This just to contrast with the typical (diffused? lateral?) Si JFETs familiar for signal purposes, which are generally symmetrical, or close (think I saw one that's 20 vs. 40V or something like that?).  And that itself is more an accident of Si JFETs in general: there used to be higher voltage types, but they disappeared quickly as BJTs were improved.  So you only see small-signal JFETs left these days.  And not many, at that...

There's also some SiC BJTs, which bizarrely they specify them like they're FETs with "gate" current... I don't even. Do people not know how to use BJTs anymore?.. :o

Anyway I digress.  The hybrid cascode ones are fine, at least from the data I've seen; I haven't used one yet.

There's also hybrid cascode GaN devices, basically so you get the same Si compatible drive level.

Cascodes reduce reverse transfer capacitance a bit.  In particular, Crss above [voltage] saturation is minuscule.  Which means output dV/dt has almost no bearing on gate resistor for example, and you're only tweaking dI/dt (and fairly crudely at that) as a result.  So keep that in mind when tweaking for EMI response.  Capacitance is still quite large at low voltages however, because the cascoded device saturates, exposing the bottom transistor's capacitance.  So it's kind of like SJ turned up to 11, an even more extreme abruptness of capacitance variation.

And mind, capacitance variation isn't necessarily a problem.  It's mainly troublesome for hard switching applications, where one transistor turns on into the other's (very large capacitance, because its voltage is still low), which acts very much like reverse recovery of a PN diode.  It's not, it's a majority carrier effect, like a schottky diode -- but the large capacitance still incurs dynamics in the switching loop which have a very similar effect in the end.

Anyway, they're fine.  They exist because you don't need to know anything special to use them, just take note of the particular characteristics (Qg, Coss, speed and losses, voltage limits, etc.).  They probably perform slightly worse than single devices, on account of added Rds(on) from the series device, and perhaps there is reason to more tightly control the main device's Vgs -- but to do that you need SiC or GaN specific drivers, so the space of gate drivers you can use with it is greatly reduced.


schmitt trigger:
As I had mentioned, I wasn’t previously aware that these devices had already existed for 7+ years.

Although the WP is glowing with respect to SiC JFET’s capabilities, if they have not become mainstream in this period, is because there are caveats to its use, or people don’t understand them sufficiently to apply them correctly. Or both.
Which one of those scenarios is the root cause? I don’t know. But the devices themselves are quite intriguing.

Tim hits the nail on the head (as usual). Main issues being resistance contribution from the Silicon low-side MOSFET, particularly at high temperatures, and lack of control of drain dV/dt by Rg are the main downsides of this technology compared to plain SiC MOSFETs. For the latter, USCi recommend using a drain RC snubber (AFAIU for functional reasons, not just EMI) with these parts. When I compared them for a commercial project, cascodes were just not competitive for our application comparing Rdson at temperature. That was a few years back and for 1200 V devices, I remember the 650 V parts looked like a better value proposition compared to other options.

One of the main marketing points for these is drive compatibility with Silicon MOSFETs and IGBTs, and I can see the advantage of this. I could see them being interesting as drop-in replacements for superjunction in 650 V applications, but this is also less of an advantage at 1200 V where IGBTs rule. Just plain substituting IGBTs for SiC in a given application is not likely to lead to a very optimal design, most of the cost and size savings are realized when magnetics are resized to rebalannce converter losses considering the usual ~85 % reduction in hard-switching losses compared to IGBTs.

One could argue that the support for GDT drive can reduce thee cost and complexity of the drive system, and this applies in some, but fewer and fewer cases. Duty cycle range with GDTs is limited on account of the volt-seconds balance, so it's mainly relevant in resonant or narrow-duty-cycle range applications. With the slew rates of SiC (and also SJMOS), current injection into the driver stage through GDT interwinding capacitance is a real concern, generally in the 50+ V/ns range. Fully isolated gate drive chips with UVLO, dead-time enforcement, good CMTI (150++ V/ns) and low cost are plentiful these days, the same goes for low-capacitance CMTI-characterized DC/DCs for gate drive power.

The devices have had success in the market, maybe not as much as plain SiC MOSFETs, but I have seen units in the field as part of mass produced DC EV chargers.

They also do plain JFETs which are pretty interesting. They don't have the Rdson contribution from the cascode FET, but they are also a bit tricky to incorporate into robust voltage-mode converter topologies as they turn on when gate power is lost. For current-fed topologies, they could be an excellent option though. I also recall hearing that they are good for protection circuits like solid state DC fuses, as their saturation behavior is more abrupt than MOSFETs, limiting current to a larger degree during overcurrents for a given voltage drop at nominal current.


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