Author Topic: LDO Output caps layout design  (Read 650 times)

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Offline Jim from Chicago

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LDO Output caps layout design
« on: January 23, 2023, 07:18:36 pm »
If I have an LDO with multiple output caps, for example 0.1uF, 1uF, 10uF, etc, should you place the largest capacitance value closest to the pins and the smaller values farther away from the pins? Or vice-versa? Or does it not really matter? (And would the same principle apply to the input caps as well)

Online T3sl4co1l

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Re: LDO Output caps layout design
« Reply #1 on: January 23, 2023, 10:07:12 pm »
LDOs are sensitive to impedance near the cutoff frequency, typically 10kHz to low MHz.  No parallel combinations are relevant at those frequencies -- just put the biggest in, or an equivalent total in parallel.

Staggered values/sizes in parallel are generally a poor idea, anyway.  It's an outdated idea, as far as I know (can be helpful with THT capacitors, but who uses those anymore).

If the LDO specifies ESR, then that ESR really only applies in the same frequency range; usually one can use a bulk cap of e.g. 10uF with nominal ESR (or a low-ESR / ceramic plus external resistor, same thing) and the little 0.1's in parallel with it only dominate at high frequencies where the LDO doesn't care.  More technically: a C1 || (R + C2) network still has ESR at middle frequencies (between f_L = 1 / (2*pi*R*C2) and f_H = 1 / (2*pi*R*C1), C1 << C2), while giving low ESR at high frequencies (C1 dominates).

Or with low ESR at the source end, you may want to add losses (another bulk cap, of nominal ESR) at the far end, to dampen possible resonances between the large (low ESR?) cap and the rest.

Or add series loss, such as a ferrite bead* or R || L, between the low-ESR bulk cap and the supply route(s).

In general, you can model the power distribution network (PDN) as series inductors (trace inductance, ~1nH/mm; include via, pad and component body lengths as well!), shunt capacitors (with some ESR and ESL, check their characteristic sheets), and the impedance of any sources and loads you have data for, or can reasonably assume (e.g. digital logic generally has a resistive V(I) characteristic; analog (op-amps and such), constant-current; etc.).

*Ferrite beads saturate (impedance curve drops) when biased with DC.  Typically they're fine for 10s to low 100s mA, depending on impedance and size.  Check the char sheets -- but beware, most manufacturers don't provide DC bias data.  (Laird, however, does for most of their catalog.)  The difference between a ferrite bead and an inductor is, the FB gives a modest and lossy (read: significant resistance) impedance to signals (read: low or zero DC bias), whereas an inductor gives a higher Q (low resistance) inductive impedance over its useful frequency range, and up to rated saturation current.  In both cases, the rated DC current is purely a thermal figure and has nothing to do with electrical behavior -- a 2A ferrite bead might saturate at 50mA, while an Isat = 2A inductor is good for any current up to that.

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Online AnalogTodd

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Re: LDO Output caps layout design
« Reply #2 on: February 04, 2023, 04:14:18 am »
Actually, there is a thought process behind using multiple values of capacitors on the output of an LDO which has to do with capacitor parasitic inductance and the net impedance of the capacitor network--it can be important when dealing with high frequency load transients, mainly when the load transients are beyond the ability of the regulator to respond to.

With that said, the question comes down to what you are powering with your LDO. Is it something that runs extremely high frequency (RF amplifier or such)? When you're talking about something like that, the parasitic trace inductance between capacitors can factor in to the ability of the network to respond to transient loads. If you're talking about a small audio amplifier (20kHz maximum) then it doesn't matter what order they go in. Same thing holds true for input capacitors.
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