LTspice simulation of two transistor forward with synchronous rectifiers

[ocset]

Hi,
Please help  to get this LTspice simulation of a two transistor forward SMPS with synchronous rectifiers working. (VIN=48V, VOUT=40V, 4A)
 It uses ….

LT1681 as the primary driver and…
LTC1698 as the synchronous rectifier controller.

Please find attached the LTspice simulation and the pdf schem.
The simulation runs terribly slow, so I have had to use an ideal transformer with no leakage in it in order to speed up the simulation. Unfortunately this results in enormous current spikes getting pulled through the CDS of the sync rect FETs   when the primary fets turn on.
Do you know why the LTC1698  has no means of sensing reverse  current in the synchronous FETs? LTC1698 only  has facility to sense  average output current.  (I haven’t set this up in the LTspice simulation as again it takes too long to run if I do.)
As you know, the main death-trap with synchronous FETs (in the 2 tran forward)  is that the inductor current can reverse through the sync fets, and then when they turn off, a huge voltage  spike gets caused across the synchronous fets. So I am amazed the LTC1698 has no means of countering this?
I  wish to put in a switch and do no-load-to-full-load testing of the LTspice simulation, but at the moment, it wont even regulate, The LTC1698 just keeps its opto output grounded even when the vout goes above 40V.

LTC1698
https://www.analog.com/media/en/technical-documentation/data-sheets/1681f.pdf

LT1681
https://www.analog.com/media/en/technical-documentation/data-sheets/1681f.pdf

[ocset]

Hi,
I have the LTspice sim working now as attached.

However, at 1.7301ms, the simulation shows the great danger of using this kind of synchronous rectifier controller...

The LTC1698 has no fast inductor current  reversal detection and  also, it allows the sync fets to stay on for more than one switching period.  Due to this, when  the 2 transistor forward is suddenly switched from full load to no load, the inductor current subsequently  reverses as the “power” sync fet switches on. The “power” sync fet is shown to stay on for 3.5 switching periods….this should never happen, but LTC1698 allows it to happen. When the power sync fet turns off at 1.7301ms, an enormous voltage spike erupts across the VDS of the “power” sync fet. This is because following the switch off of the “power” sync  fet in which reversed inductor current is flowing, the inductor current has nowhere to flow….hence the massive overvoltage.

This is why these type of Synchronous fet controllers should have a  severe health warning on their datasheet.   

At the very least…these type of sync fet controllers should always be implemented with  suitable TVS’s across the sync fets……however, the TVS capacitance is not welcome as it will ring with the secondary referred leakage inductance.

Really, these type of sync  fet controllers should only be implemented in conjunction with load current detection circuitry. That is, when the load current suddenly falls below say 25% (or whatever level would lead to DCM  in  the equivalent  non sync fet  design), then the sync fet controller should be immediately disabled. With LTC1698, this would mean driving the sync fets from external gate drive ICs and  then  pulling their resistor fed inputs  to ground  in order to disable them. This could affect primary/secondary switching  interleaving timings…so this also means that a similar external gate driver IC should be used to delay the primary side fet switchings.
Another way would be to have a dedicated microcontroller to "watch" the sync fet gate drives, and  disable them if they remain on for more than one switching period.
And i believe...also have a backdrop TVS across the syn fet just to be sure.

The only topology that’s cast-iron safe with synchronous rectifiers is the Buck converter…because if the buck sync fet is turned off whilst reverse inductor current is flowing in it…then the inductor current simply starts to harmlessly flow through the diode across the Buck power fet, and into the input capacitor.

These sync fet controllers are absolute death traps for the uninitiated. 

Who else makes sync rect controller chip set pairs for two transistor forward?   
Why do so few IC co's make them?...is it because of these issues highlighted here? 

I am not knocking them….as discussed, if the above mentioned  additions are made to the circuit, then they are do-able.

[ocset]

Actrually, adding RCD  clamps across the sync FETs does solve the problem with the LT1681/LTC1698 combo. As  attached.
In fact, the lack of the usual fast current sense (with the LTC1698)  now makes me think this solution may be  better than others which have fast sync rect current sense….since with the low sense thresholds on offer, they look like noise disasters waiting to happen.
I think I would add a TVS across the clamp capacitor too.
Any ideas why these seemingly essential additions aren’t  advised on the LTC1698 datasheet? 

[dietert1]

I don't know the LTC1698 very well, but i'd like to confirm that you cannot reliably detect current reversal when running a rectifier FET in switched mode.

One or two years ago in a small project i found that i needed to use the FETs in linear mode. If you think about the typical conduction voltage of a silicon rectifier of 1 V and a schottky rectifier 0.5 V, then you can make the FET a rectifier of 20 mV conduction voltage. Linear regulators for the conduction voltage were the best approach i found. With sub-milliohm FETs and high peak currents i didn't want those extra current measurement resistors.

Regards, Dieter

[ocset]

Thanks, that sound slike a cracking idea....using a FET as a linear current regulator in order to stop  reversing overcurrents in a sync rect forward converter.