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Negative FET/IGBT gate drive to stop spurious turn ON

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Siwastaja:
So-called "miller clamp" is also available in some gate drivers. Basically it just bypasses the Rg after switching is complete so you can have both the controlled switching time, yet stronger lower-impedance driver keeping the gate steady when the another transistor in the bridge is switching and causing trouble by dV/dt coupling through Cgd.

You can of course combine such "miller clamp" and negative gate bias.

Whatever measures are needed completely depend on the parts and circuit used, you can't universally say what is needed and what is not. Simulating in Spice is highly recommendable, assuming you have accurate models available.

David Hess:

--- Quote from: MasterTech on October 19, 2021, 01:29:48 pm ---All those oscillations you see on Vgs are not real. They are common mode distortion typical in differential probes. For the low side you could use a x10 single ended probe if the ground is shared. For the upper you won't know until you use a fiber isolated probe.
--- End quote ---

When using differential probes like that, I always double check the common mode error by also making the measurement with both leads connected to the source/emitter.  Then the measured signal should be zero but the common mode error will be revealed.

The same sort of test applies to single ended probes to reveal ground loop errors.

ElectricEffects:

--- Quote from: MasterTech on October 19, 2021, 01:29:48 pm ---All those oscillations you see on Vgs are not real. They are common mode distortion typical in differential probes. For the low side you could use a x10 single ended probe if the ground is shared. For the upper you won't know until you use a fiber isolated probe.
And the 10V Vds false turn-off, not sure, is pretty low in level and slow in speed

--- End quote ---

The oscillations is still there, specially in the dead time period. In fact using a single-ended probe (@500MHz with short ground lead) my converter works with more interference and lower efficiency. The results of Vgs spikes are almost the same with the differential probe (tektronix T5200A 50MHz and +-1300 commom voltage).

The high impedance of the diff probe did not interference with both my hard switching converter and the LLC with soft switching. Anyone else had problems with this single ended probe?

T3sl4co1l:

--- Quote from: ElectricEffects on October 19, 2021, 12:23:00 pm ---It's my first SiC design, have a lot to learn. I see oscillations in the dead time period and changing Cgs(external) to 2nF starts to appear higher oscillations in VDS for low loads and even low voltages.

--- End quote ---


--- Quote ---I'm using the Cree Ref design and they put the 1nF cap, I supose this improves the CMTI of the GD CI. If more problems appear, this cap for sure is gonna be removed.

The image below shows this Cgd oscillations causing a little false turn-off.

--- End quote ---

Please confirm, Cgd or Cgs?  I was about to ask if that was a typo, but...

Which ref design?  In SCH_CRD-20DD09P-2 V3.pdf I see 1nF G-S and 100pF D-S.  I don't get the G-S, that again tends to be an invitation for oscillation, but it's certainly not G-D.

In https://assets.wolfspeed.com/uploads/2020/12/CPWR_AN27.pdf , I see two 1nF's G-S actually, though I don't know at a glance why there's two gate terminals, maybe it's a footprint option.  And the antiparallel diodes will have some capacitance I suppose.

Doesn't seem to be much else for demo boards, at least linked from the part you're using.  I don't know where else you'd be getting that from...

Tim

Phoenix:

--- Quote from: T3sl4co1l on October 20, 2021, 01:16:11 am ---In https://assets.wolfspeed.com/uploads/2020/12/CPWR_AN27.pdf , I see two 1nF's G-S actually, though I don't know at a glance why there's two gate terminals, maybe it's a footprint option.

--- End quote ---

The board fits both the 3 pin and 4 pin (kelvin source) version of TO-247. It describes moving the FB to change between then so only one of the 1nF GS capacitors is in circuit at any time.

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