Electronics > Power/Renewable Energy/EV's

Negative FET/IGBT gate drive to stop spurious turn ON

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It's Cgs, my mistake.
I didn't get the results with Cgs(external) = 2nF. The V(ds) had those oscillations and for another mistake I destroyd 3 MOSFETS, then return the capacitance to 1nF.

How about changing the capacitance to zero like it should be, and measure the source current to check for overload?


--- Quote from: uer166 on October 21, 2021, 01:41:28 am ---How about changing the capacitance to zero like it should be, and measure the source current to check for overload?

--- End quote ---

I found an article explanning this Cgs(external). "Improving the performance of SiC trench MOSFETs under hard switching operation"

--- Quote ---In Fig. 2, one can see the turn-off losses vs. stray inductance split up into di/dt- and du/dt-losses at rated module current in (a) and at half the rated current IN in (b). At rated module current the transistor turn-off losses are mainly dissipated during the di/dt-phase of the switching transient, while at half the rated current the share of du/dt in Eoff is dominant. For this reason, by adding an external gate-source capacitor, as done in Fig. 8, the du/dt-phase of the switching transient is accelerated without changing the di/dt. In order to achieve this RG,ext is reduced, see Fig. 9. The damping resistor RC is added to avoid oscillation between CGS,ext and CGS.
The resulting waveforms for transistor turn-off and turn-on can be seen in Fig. 9. There it can be seen that at turn-off the du/dt-time is reduced by adding CGS,ext without affecting di/dt and hence overvoltage. The time constant of the gate-voltage measured at the terminals of the power module remains unchanged, see Fig. 9(b) and (d), but with the change towards lower gate resistance and higher capacitance the gate current increases. As a result the miller time is shorter and du/dtlosses are cut in half with result in a total decrease of the turnoff losses by 26%.

--- End quote ---

I'm not showing the figs, but the series resistor put in the Cgs(external) is Rc = 1/2*Rg,int and Cgs(ext) = 2*Ciss. This Rc might prevent my oscillations.

I'm not being tough, but in my design it's quite hard to remove this capacitor and I agree there's benefits of doing that especially when not using Miller Clamp GD.
My 3-phase boost is working at low voltages, if more problems starts to appear at higher power levels this Cgs(ext) for sure may be removed.

This is the voltage and line current for phase A.


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