Electronics > Power/Renewable Energy/EV's

Negative FET/IGBT gate drive to stop spurious turn ON

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Faringdon:
Hi,
As you know, SMPS's with stacked FETs as in full bridge's, synchronous Bucks, suffer spurious turn on of a fet in a leg when the other fet turns on.......causing shoot thru current.
How much does a negative turn off gate drive help to reduce this?

Eg if the gate is sitting down at -5V , then surely its far less likely to get spuriously turned ON?

Isnt Negative gate drive almost mandatory for IGBTs in BLDC inverter drives?

ahbushnell:
I know large IGBT's and SiC MOSFET's require negative bias in the data sheets. Follow manufacturers recommendations. 

David Hess:

--- Quote from: Faringdon on September 04, 2021, 08:25:47 pm ---As you know, SMPS's with stacked FETs as in full bridge's, synchronous Bucks, suffer spurious turn on of a fet in a leg when the other fet turns on.......causing shoot thru current.
--- End quote ---

That cannot be universally true.  Plenty of designs use dead-time between turning one FET off and one FET on to avoid shoot-through.  One clever way is to monitor the gate voltages and only switch the other transistor when the gate voltage is below the plateau voltage; Linear Technology does this.

Faringdon:
Thanks, yes i am referring to a fet being spuriously turned on by the switching of its "paired fet", well after its VGS went to zero.

David Hess:

--- Quote from: Faringdon on September 05, 2021, 09:50:53 am ---Thanks, yes i am referring to a fet being spuriously turned on by the switching of its "paired fet", well after its VGS went to zero.
--- End quote ---

If that is caused by excessive dV/dT triggering the parasitic bipolar, then the gate voltage is irrelevant.  That looks like the off MOSFET is turning on but it is not and this can quickly result in destruction of the MOSFET.

Holding the gate negative will help when the gate-to-drain capacitance is what is turning it on, but so would lowering the impedance of the gate drive circuit.

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