Negative FET/IGBT gate drive to stop spurious turn ON

[Faringdon]

Hi,
As you know, SMPS's with stacked FETs as in full bridge's, synchronous Bucks, suffer spurious turn on of a fet in a leg when the other fet turns on.......causing shoot thru current.
How much does a negative turn off gate drive help to reduce this?

Eg if the gate is sitting down at -5V , then surely its far less likely to get spuriously turned ON?

Isnt Negative gate drive almost mandatory for IGBTs in BLDC inverter drives?

[ahbushnell]

I know large IGBT's and SiC MOSFET's require negative bias in the data sheets. Follow manufacturers recommendations. 

[David Hess]

As you know, SMPS's with stacked FETs as in full bridge's, synchronous Bucks, suffer spurious turn on of a fet in a leg when the other fet turns on.......causing shoot thru current.

That cannot be universally true.  Plenty of designs use dead-time between turning one FET off and one FET on to avoid shoot-through.  One clever way is to monitor the gate voltages and only switch the other transistor when the gate voltage is below the plateau voltage; Linear Technology does this.

[Faringdon]

Thanks, yes i am referring to a fet being spuriously turned on by the switching of its "paired fet", well after its VGS went to zero.

[David Hess]

Thanks, yes i am referring to a fet being spuriously turned on by the switching of its "paired fet", well after its VGS went to zero.

If that is caused by excessive dV/dT triggering the parasitic bipolar, then the gate voltage is irrelevant.  That looks like the off MOSFET is turning on but it is not and this can quickly result in destruction of the MOSFET.

Holding the gate negative will help when the gate-to-drain capacitance is what is turning it on, but so would lowering the impedance of the gate drive circuit.

[Phoenix]

Isnt Negative gate drive almost mandatory for IGBTs in BLDC inverter drives?

It's certainly an easy (generally) and effective option, especially for IGBTs and definitely recommended by manufacturers for modules.

Some other options:

1. Faster/stronger turn-off (using extra turn off diode and resistor). This helps the gate driver hold the voltage low. If you just lower the single resistor you will get also get a faster turn-on dv/dt negating some of the benefit of stronger turn-off.
2. Negative voltage rail. This gives more headroom for the miller spike before threshold. Many SiC FETs don't like negative rail drives, it significantly reduces their lifetime [1].
3. Miller clamp. Provides a shorting transistor very close to the gate-source without resistance that only turns-on once the switch is actually off.
4. Additional gate capacitance. The miller spike magnitude is determined by the ratio of miller capacitance and gate capacitance. If you increase gate capacitance you lower the spike. But you will need to drive more gate current for the same turn-on/off times.

Other Considerations:

1. Gate drive loop inductance. More inductance means the gate driver itself will have less bandwidth to hold off a high speed spike.
2. Boot strap high side supply doesn't easily create a negative rail.
3. There are many many app notes on this topic!

Thus a negative rail is not always mandatory (and SiC manufacturers even warn against). But if you already have isolated gate drive supplies it's very easy to add.

[1] Infineon AN2018-09

[ElectricEffects]

I'm working on a three-phase PFC boost rectifier and the first tests was performed using a DC-DC PSU with current limitting capability.
I'm using C3m0120100K with RGon = 30 ohms, RGoff = 25 ohms, Cgd = 1nF. I'd more confident using lower RG with 4 layer layout and a miller clamp gate driver.

I measured the Vgs lower and upper with long "inductive" differential probes. The purple channel didn't show overshoot and a rise time of aprox. 40ns.
It's also possible to see the di/dt of one phase disturbing the upper Vgs signal. 



Forgot to mention, it's almost mandatory to place a 1uF - 2.2uF capacitor as close as possible to the paired FET to sink the didt. You can see Cree reference design for better undestanding.
 

[T3sl4co1l]

Cgd as in an intentionally added part??

Tim

[ElectricEffects]

Yes, actually Cgd(external) = 1nF. This SiC has around 400pF of Ciss.

My first results were without the 1uF across the FET pair and it was impossible to make it work due to the Vgs oscilations with more than 2A.

[uer166]

Yes, actually Cgd(external) = 1nF. This SiC has around 400pF of Ciss.

My first results were without the 1uF across the FET pair and it was impossible to make it work due to the Vgs oscilations with more than 2A.

External Cgd is bad for SiC because its' ringing does not get damped/limited by your Rg. The advice I saw from SiC mfg was to control the rise/fall by the Rg value only, and rely on internal Cgd, since any oscillation is damped this way..

[T3sl4co1l]

But why?

In general, putting any capacitance around the gate terminal of a MOSFET is setting up for oscillation.  Cgd in particular is setting up for increased switching loss -- or if it's unstable, oscillation, or chatter like you see here -- since after all, that's precisely how Miller effect works, it works by turning on the device and thus acting to slow the rise.  You're literally injecting switching loss into the system; I'm not sure how else to read it but: "yup, that seems to be what you wanted to do".

When cascoding devices (for higher standoff voltage ratings), some capacitance may be desirable, to distribute the voltage especially during switching; and this may increase switching loss (of course there will be a price to pay for that increased voltage handling).  Damping resistors are recommended, so that under transient conditions, the drain feedback forms a divider with the gate drive, while dampening oscillatory modes.

Tim

[PartialDischarge]

It's also possible to see the di/dt of one phase disturbing the upper Vgs signal. 

I don’t think it is di/dt related but common mode interference from the diff probes.

[ElectricEffects]

External Cgd is bad for SiC because its' ringing does not get damped/limited by your Rg. The advice I saw from SiC mfg was to control the rise/fall by the Rg value only, and rely on internal Cgd, since any oscillation is damped this way..

It's my first SiC design, have a lot to learn. I see oscillations in the dead time period and changing Cgs(external) to 2nF starts to appear higher oscillations in VDS for low loads and even low voltages.

But why?

In general, putting any capacitance around the gate terminal of a MOSFET is setting up for oscillation.  Cgd in particular is setting up for increased switching loss -- or if it's unstable, oscillation, or chatter like you see here -- since after all, that's precisely how Miller effect works, it works by turning on the device and thus acting to slow the rise.  You're literally injecting switching loss into the system; I'm not sure how else to read it but: "yup, that seems to be what you wanted to do".

When cascoding devices (for higher standoff voltage ratings), some capacitance may be desirable, to distribute the voltage especially during switching; and this may increase switching loss (of course there will be a price to pay for that increased voltage handling).  Damping resistors are recommended, so that under transient conditions, the drain feedback forms a divider with the gate drive, while dampening oscillatory modes.

Tim

I'm using the Cree Ref design and they put the 1nF cap, I supose this improves the CMTI of the GD CI. If more problems appear, this cap for sure is gonna be removed.

The image below shows this Cgs oscillations causing a little false turn-off.

[PartialDischarge]

All those oscillations you see on Vgs are not real. They are common mode distortion typical in differential probes. For the low side you could use a x10 single ended probe if the ground is shared. For the upper you won't know until you use a fiber isolated probe.
And the 10V Vds false turn-off, not sure, is pretty low in level and slow in speed

[ahbushnell]

Yes, actually Cgd(external) = 1nF. This SiC has around 400pF of Ciss.

My first results were without the 1uF across the FET pair and it was impossible to make it work due to the Vgs oscilations with more than 2A.

External Cgd is bad for SiC because its' ringing does not get damped/limited by your Rg. The advice I saw from SiC mfg was to control the rise/fall by the Rg value only, and rely on internal Cgd, since any oscillation is damped this way..

We normally tune the gate resistor to control the ringing.  Start a little low and work your way up.  I would not add capacitance on the gate. 

[Siwastaja]

So-called "miller clamp" is also available in some gate drivers. Basically it just bypasses the Rg after switching is complete so you can have both the controlled switching time, yet stronger lower-impedance driver keeping the gate steady when the another transistor in the bridge is switching and causing trouble by dV/dt coupling through Cgd.

You can of course combine such "miller clamp" and negative gate bias.

Whatever measures are needed completely depend on the parts and circuit used, you can't universally say what is needed and what is not. Simulating in Spice is highly recommendable, assuming you have accurate models available.

[David Hess]

All those oscillations you see on Vgs are not real. They are common mode distortion typical in differential probes. For the low side you could use a x10 single ended probe if the ground is shared. For the upper you won't know until you use a fiber isolated probe.

When using differential probes like that, I always double check the common mode error by also making the measurement with both leads connected to the source/emitter.  Then the measured signal should be zero but the common mode error will be revealed.

The same sort of test applies to single ended probes to reveal ground loop errors.

[ElectricEffects]

All those oscillations you see on Vgs are not real. They are common mode distortion typical in differential probes. For the low side you could use a x10 single ended probe if the ground is shared. For the upper you won't know until you use a fiber isolated probe.
And the 10V Vds false turn-off, not sure, is pretty low in level and slow in speed

The oscillations is still there, specially in the dead time period. In fact using a single-ended probe (@500MHz with short ground lead) my converter works with more interference and lower efficiency. The results of Vgs spikes are almost the same with the differential probe (tektronix T5200A 50MHz and +-1300 commom voltage).

The high impedance of the diff probe did not interference with both my hard switching converter and the LLC with soft switching. Anyone else had problems with this single ended probe?

[T3sl4co1l]

It's my first SiC design, have a lot to learn. I see oscillations in the dead time period and changing Cgs(external) to 2nF starts to appear higher oscillations in VDS for low loads and even low voltages.

I'm using the Cree Ref design and they put the 1nF cap, I supose this improves the CMTI of the GD CI. If more problems appear, this cap for sure is gonna be removed.

The image below shows this Cgd oscillations causing a little false turn-off.

Please confirm, Cgd or Cgs?  I was about to ask if that was a typo, but...

Which ref design?  In SCH_CRD-20DD09P-2 V3.pdf I see 1nF G-S and 100pF D-S.  I don't get the G-S, that again tends to be an invitation for oscillation, but it's certainly not G-D.

In https://assets.wolfspeed.com/uploads/2020/12/CPWR_AN27.pdf , I see two 1nF's G-S actually, though I don't know at a glance why there's two gate terminals, maybe it's a footprint option.  And the antiparallel diodes will have some capacitance I suppose.

Doesn't seem to be much else for demo boards, at least linked from the part you're using.  I don't know where else you'd be getting that from...

Tim

[Phoenix]

In https://assets.wolfspeed.com/uploads/2020/12/CPWR_AN27.pdf , I see two 1nF's G-S actually, though I don't know at a glance why there's two gate terminals, maybe it's a footprint option.

The board fits both the 3 pin and 4 pin (kelvin source) version of TO-247. It describes moving the FB to change between then so only one of the 1nF GS capacitors is in circuit at any time.

[ElectricEffects]

It's Cgs, my mistake.
I didn't get the results with Cgs(external) = 2nF. The V(ds) had those oscillations and for another mistake I destroyd 3 MOSFETS, then return the capacitance to 1nF.

[uer166]

How about changing the capacitance to zero like it should be, and measure the source current to check for overload?

[ElectricEffects]

How about changing the capacitance to zero like it should be, and measure the source current to check for overload?

I found an article explanning this Cgs(external). "Improving the performance of SiC trench MOSFETs under hard switching operation"

In Fig. 2, one can see the turn-off losses vs. stray inductance split up into di/dt- and du/dt-losses at rated module current in (a) and at half the rated current IN in (b). At rated module current the transistor turn-off losses are mainly dissipated during the di/dt-phase of the switching transient, while at half the rated current the share of du/dt in Eoff is dominant. For this reason, by adding an external gate-source capacitor, as done in Fig. 8, the du/dt-phase of the switching transient is accelerated without changing the di/dt. In order to achieve this RG,ext is reduced, see Fig. 9. The damping resistor RC is added to avoid oscillation between CGS,ext and CGS.
The resulting waveforms for transistor turn-off and turn-on can be seen in Fig. 9. There it can be seen that at turn-off the du/dt-time is reduced by adding CGS,ext without affecting di/dt and hence overvoltage. The time constant of the gate-voltage measured at the terminals of the power module remains unchanged, see Fig. 9(b) and (d), but with the change towards lower gate resistance and higher capacitance the gate current increases. As a result the miller time is shorter and du/dtlosses are cut in half with result in a total decrease of the turnoff losses by 26%.

I'm not showing the figs, but the series resistor put in the Cgs(external) is Rc = 1/2*Rg,int and Cgs(ext) = 2*Ciss. This Rc might prevent my oscillations.

I'm not being tough, but in my design it's quite hard to remove this capacitor and I agree there's benefits of doing that especially when not using Miller Clamp GD.
My 3-phase boost is working at low voltages, if more problems starts to appear at higher power levels this Cgs(ext) for sure may be removed.

This is the voltage and line current for phase A.