If you're getting orders-of-magnitude increases in simulation time, something is very wrong! Those options are increasing the element count by one, three and about a dozen, respectively.
Not at all - making k<1 or specifying meaningful parallel capacitance results in high frequency ringing which drastically increases the amount of data generated and (should) force the simulator to reduce the time step size. That said, I did fail to mention that one has to actually tell LTSpice to limit the size of the time step when incorporating real strays otherwise it might just skip right over the oscillations caused by them completely.
To get waveforms "exactly like ... the prototype" you'd likely have to run FEA on the layout itself
Yep, but that's what most of here are arguing isn't worth the effort!? I was just using SPICE simulation of the circuit to extrapolate the immense increase in difficulty required to do an FE analysis of the entire assembly for EMC (that is the subject of this thread, after all...
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...you're also depending on the manufacturer device models, which vary from stock SPICE (e.g. a LEVEL=3 MOSFET with nonlinear capacitors and parasitics added on) to full-on custom (2-3 pages solid of nonlinear dependent sources and their functions). The former runs fast and converges well but misses subtle physics of the real device; the latter runs terribly slow on board-level simulators, and may suffer from convergence issues, especially in buggy simulators (possibly the enterprise-level ones do better, or at least take better advantage of more powerful hardware).
Yep, we're on the same page here. Experience, knowledge and good judgement (oh, and time) inform when to do the quick-n-dirty sim vs. when to use the full blown subckt/inline models for every component, etc. The thing is, for circuit simulation you can often do the quick-n-dirty for most of the development process and only switch to using the device-specific models when fine-tuning things, but for EMC simulation you need to specify Every Fucking Thing or doing it is pointless.
Taking the statement at face value, it's believable, but has the issues I identified. Now that you've identified the particular case, I can see it is indeed on the realistic side.
Sorry for being circumspect but NDAs and all that. I can't even mention the specific topology without giving away what the thing is since the author of the IEEE paper on it is the lead engineer at the company.
At any rate, yes, the problem is, indeed, incomplete knowledge of all the salient - if not the passingly relevant - details involved. But like I said above, that's not necessarily fatal when doing a SPICE simulation of a circuit, but invariably fatal when doing an FE analysis for EMC.
Yep, that's a problem for anyone new to a given field or sub-field: you simply don't have experience in the particulars. Doesn't matter how smart or educated you are; if you don't have that exact experience, you simply don't. Ignorance isn't a bad thing, it's just a thing. You can't fix stupid, as they say, but ignorance is easily treated through research and practice.
Right... you meant literal ignorance - a simple lack of knowledge - rather than the altogether more pejorative meaning commonly ascribed to it today. We're in total agreement there, then. I still maintain that FEA (or FEM - whether you prefer the last letter stand for Analysis or Modeling) is economically unattractive most of the time. I mean, have you actually used (or tried to use) SABER or ANSYS (for two examples I've had the displeasure of being tortured with before)? Those programs just have the most brutal learning curve of anything I have ever seen.
A good approach would be to do an introductory project or two, to feel out the new space Then to dive into the big project, being able to optimize everything much more evenly, not just the core-domain parts. Sometimes that may not be possible due to tight schedules; then again, it could well be a time saver yet, even if not to the immediate deadline, but to avoid inevitable production delays later on.
Mmm... yep, I agree this is the best way to get up to speed with such FEA monstrosities, but in this case it is 2.5 years past the original estimate of taking 6 months to complete... But baptism-by-fire is the usual way things get done in small companies.