PCMC+PSFB on STM32 is it possible?

[Alex-lab]

Hi,

Up to now I have been using STM32G4 to control phase-shift full-bridge (PSFB) in voltage control mode (VCM). Now I would like to add peak current control mode (PCMC) for better performance, but it appears that none of STM32G4 is capable with such capabilities. At least I was unable to find the way for it.
Did I miss something? What is the best way for such digitally controlled power supply?
I have thought about some hybrid, a digital+analogue approach by coupling STM32 with something like UC28950, but I still believe that should be a better way...

Thanks,

[fourtytwo42]

I also found the STM32 PWM poor in terms of facilities and adaptability, of course they use the same block of IP in all there offerings so they are all the same.
I thought of pairing it with an FPGA but that's getting expensive so in the end I changed to the motor control variety of the PIC24EP series, unfortunately a different IDE and programmer/debugger to pay for.

[uer166]

Hi,

Up to now I have been using STM32G4 to control phase-shift full-bridge (PSFB) in voltage control mode (VCM). Now I would like to add peak current control mode (PCMC) for better performance, but it appears that none of STM32G4 is capable with such capabilities. At least I was unable to find the way for it.
Did I miss something? What is the best way for such digitally controlled power supply?
I have thought about some hybrid, a digital+analogue approach by coupling STM32 with something like UC28950, but I still believe that should be a better way...

Thanks,

HRTIM with reset event inputs (for your peak current limit) should be able to do this, the regular advanced timers are way too limiting. Have you looked into that peripheral?

[mtwieg]

At a glance at the reference manual, it looks like the STM32G4 has all the requisite building blocks for doing current mode control:
1. PWM synthesis controlled by external events
2. Analog comparators which can generate events for the PWM synthesis based on the sensed current
3. DACs which can connect to the inputs of the comparators (12 bits should be sufficient)
4. DACs can be set up to generate ramp/sawtooth waves to implement slope compensation

I've worked a lot with C2000 MCUs which are aimed at such applications, and the feature set looks comparable. Actually configuring these peripherals to work together properly is definitely not straightforward though. I would hope that STM's documentation is better than TI's...

[Siwastaja]

At a glance at the reference manual, it looks like the STM32G4 has all the requisite building blocks for doing current mode control:
1. PWM synthesis controlled by external events
2. Analog comparators which can generate events for the PWM synthesis based on the sensed current
3. DACs which can connect to the inputs of the comparators (12 bits should be sufficient)
4. DACs can be set up to generate ramp/sawtooth waves to implement slope compensation

Yes. First time I did this (on STM32F334), all of the mentioned* many years ago setting it all up wasn't too difficult, in principle... just that ST, as usual, has some silicon bugs/undocumented "features" such as some invert bit here not doing anything at, and some other bit there completely breaking non-related IO pin... So before committing to a large batch of unmodifiable PCBs, do a prototype first. Which hopefully is quite obvious anyway.

It's all in the reference manual, just build a prototype (around devboard, or spin an early revision of the actual board) and read the related sections on the reference manual and start working.

*) expect that instead of slope compensation, which I did not need due to by-design <50% duty cycle, I used the DACs for arbitrary current waveform generation

[Alex-lab]

Thank you for all replies. I was trying to setup HRTIM in a proper operation mode, but found some weird description in the refmanual (rev.8, chapter 27.3.9, p.879-880).
I would like to use blanking as highlighted by yellow colour, and struggling with its operation. The example, which is given in the text (green), is quite confusing because none of the timers (B or C) has TIMFLTR6 as output of any Tx2. Do I understand this table correctly? Is this typo in the table or in the example? May other numbers be also inaccurate?
Thanks for any ideas.

[multipla]

If you have a working PCB with the controller or a dev board already, I would also suggest trying out how the slope looks like first.
I have tried using the internal DAC of an NXP KV44 to create the setpoint and subtract a slope from it, but there were lots of glitches when many bits of the DAC word changed (midpoint glitches). This was unusable for PCMC, I ended up adding the slope externally before feeding it to an external comparator. The internal comparator had quite long and inconsistent delay times too, depending on the operating point.

[Alex-lab]

Although the table is still unclear. It seems that the basic operation was achieved.

I am using G474RET6 based Nucleo board and Arduino.
Below is my basic peripheral configuration, the pins highlighted in blue are available for probing and behave generally as expected:

As I didn't have a real device, I had to make a gyrator-based inductor current emulator:

Some important registers:

Waveform examples:

If you have a working PCB with the controller or a dev board already, I would also suggest trying out how the slope looks like first.

Not completely sure, but for me the slope looks as expected (see above). However, I worry about that additional short spikes in the output signal of CH_C1/2, which are shown in the last attachment.
I was trying to play with hysteresis, event counter filter etc., but was unable to get rid of them even for a simple desktop layout without any power conversion and any serious noise.

[mtwieg]

Is sounds like you were successful implementing a voltage-mode phase shifted bridge, and now you want to modify it to do peak current mode control. But I suspect rather than modifying what you have, you should start from scratch.

For example, is there some reason you're using center-aligned/up-down count mode for counters A and C? Using up-count mode might make things a lot simpler. I don't believe center-aligned operation has any benefit for peak CMC.

[Alex-lab]

Is sounds like you were successful implementing a voltage-mode phase shifted bridge, and now you want to modify it to do peak current mode control.

Why is not this a current mode?

[mtwieg]

Why is not this a current mode?

.... what?

You said this:

Up to now I have been using STM32G4 to control phase-shift full-bridge (PSFB) in voltage control mode (VCM). Now I would like to add peak current control mode (PCMC) for better performance

I'm saying you shouldn't "add" preak CMC to the VMC design, but instead redesign it with peak CMC in mind.

[Alex-lab]

I'm saying you shouldn't "add" preak CMC to the VMC design, but instead redesign it with peak CMC in mind.

Ok, this is exactly what I showed in my previous post as previously I used regular Timer, but now it's using HRTIM.

[mtwieg]

Ok, then why are you using center-aligned mode? I'm not an expert on STM's HRTIM, but in general I've found center-aligned operation to come with more limitations. As far as I can tell, all of STM's documentation suggests using single-slope mode for peak CMC as well.

[Alex-lab]

As ST does not provide any relevant examples for full bridge phase shift designs, I had to use an example from TI (TIDM-02000), where up-down mode is the core of the approach.
In up-down you can differentiate the front and end of the pulse explicitly (one relates to UP, another to DOWN direction). Then you add a toggle function driven by external event (comparator) and that's it.  I am not saying that with single-slope you cannot achieve similar operation, but it is definitely more complex as requires special measures.

TIDM-02000 shows the circuit, and for me it is not quite clear, why they used a full bridge rectifier for current transformer, if it is operated in unipolar mode?

[mtwieg]

As ST does not provide any relevant examples for full bridge phase shift designs, I had to use an example from TI (TIDM-02000), where up-down mode is the core of the approach.

Interesting, I don't quite understand why they would use up-down mode for this, I'm guessing it somehow makes implementing their synchronous rectifier control easier.

In up-down you can differentiate the front and end of the pulse explicitly (one relates to UP, another to DOWN direction).

The action qualifier (AQ) submodule in the C2000 ePWM modules do recognize the counter direction in determining actions, but I don't know if HRTIM has equivalent functionality. I also don't see why you'd need to differentiate the edges of the pulse in such a way.

I am not saying that with single-slope you cannot achieve similar operation, but it is definitely more complex as requires special measures.

I doubt it, but it depends on exactly how the underlying PWM logic works.

For example, you said you were struggling to implement blanking. In the C2000 design, this is done using the digital compare (DC) submodule, which is IMO by far the most complicated and confusing aspect of the entire ePWM module (I usually don't make use of any of the digital compare functions, but just configuring it to pass events through is insanely complicated). I highly doubt the HRTIM works in a similar way. You should look at how HRTIM implements blanking and start from there.

TIDM-02000 shows the circuit, and for me it is not quite clear, why they used a full bridge rectifier for current transformer, if it is operated in unipolar mode?

Agreed, that is strange. I wonder how the magnetizing flux is reset properly...

[Alex-lab]

why you'd need to differentiate the edges of the pulse in such a way.

I suppose, it is because on the over current event we need to toggle the output states, but on the normal ending (if no comp event) we should switch outputs to specific levels.
All other things like blanking and slope compensation using DAC are simple in implementation. My question was about a particular table from the manual, but it seems work fine.

Agreed, that is strange. I wonder how the magnetizing flux is reset properly...

In my future design I am planning to use unipolar circuit as in the datasheet for UCC28950.

[Alex-lab]

I am wondering if I need to change the slope magnitude for low duty cycle? I know that the DAC value controls the peak current, but what is about the slope at low duty cycle? Some appnotes (SLUA837) states that it is a good thing to have slope compensation even at low duty cycles. Despite it is mainly designed for 50% and over. Just for more predictable behaviour in noisy environment etc. May it be practical to reduce the slope at low duty cycles?

[mtwieg]

I am wondering if I need to change the slope magnitude for low duty cycle? I know that the DAC value controls the peak current, but what is about the slope at low duty cycle? Some appnotes (SLUA837) states that it is a good thing to have slope compensation even at low duty cycles. Despite it is mainly designed for 50% and over. Just for more predictable behaviour in noisy environment etc. May it be practical to reduce the slope at low duty cycles?

It's been a while since I looked closely at the math of slope compensation/subharmonic oscillation. Yes, having some slope compensation can be beneficial even when D<50%. The D>=50% threshold is based on the assumption that there are no delays in the system. For example if your controller has a delay equivalent to 5% of a PWM period, then you should have slope compensation at D>=45%. Having a bit of slope compensation might be justifiable, but I would rely on thorough empirical testing.

Changing the slope dynamically will act as a perturbation to the system, so I would not take that approach unless you've modeled everything correctly and can show a clear benefit.

[Alex-lab]

Thanks. For now I just keep it constant and it works as expected. Really impressive set point step response!

But I have one more question. Previously, working in voltage mode, when controller reduced the duty cycle below a certain minimum level (<3%), the PWM signal was shut down to zero and overall converter was turned into a "period skipping" mode.

Using PCM control I have no direct access to the current duty cycle value, thus cannot implement the same period skipping approach. As a result, when pulses are getting shorter than some critical value, the phase of variable leg jumps by ~180 deg., which cause almost 100% power. It looks like comparator is triggered twice.
Of course, this behaviour is unwanted as can easily damage the device.
What can be used as a parameter to prevent this situation?
I tried to use DAC value, to skip period if it goes below some small value (<5%), it skips periods, but the phase is still inverted...
May extended Blanking of current transformer signal help in this case?
Is there any special name for this situation?
Thank you.

[mtwieg]

But I have one more question. Previously, working in voltage mode, when controller reduced the duty cycle below a certain minimum level (<3%), the PWM signal was shut down to zero and overall converter was turned into a "period skipping" mode.

Using PCM control I have no direct access to the current duty cycle value, thus cannot implement the same period skipping approach. As a result, when pulses are getting shorter than some critical value, the phase of variable leg jumps by ~180 deg., which cause almost 100% power. It looks like comparator is triggered twice.
Of course, this behaviour is unwanted as can easily damage the device.
What can be used as a parameter to prevent this situation?
I tried to use DAC value, to skip period if it goes below some small value (<5%), it skips periods, but the phase is still inverted...
May extended Blanking of current transformer signal help in this case?
Is there any special name for this situation?
Thank you.

Hmm could you show an example waveform of what you're seeing?

The first thing that comes to mind is that your blanking is implemented such that transitions in the current comparator are ignored during the blanking window. This is as opposed to the transitions being delayed until the end of the blanking window. The former case can lead to issues like what you describe (but it's probably not the only way).

If possible I would also add a second current comparator whose threshold is always higher (maybe at the maximum peak current spec) than the first comparator, in order to limit peak current to a sane value in case the first comparator is missed. At least as a hack until a better solution is found.

If this is your problem, and there's no way to make the blanking delay the comparator trip, then another workaround may be to implement a minimum

[multipla]

But I have one more question. Previously, working in voltage mode, when controller reduced the duty cycle below a certain minimum level (<3%), the PWM signal was shut down to zero and overall converter was turned into a "period skipping" mode.

Maybe you could use the same concept in PCMC, but instead of the duty cycle you base this on when the peak current set point gets below a certain threshold and start skipping pulses then?
A blanking might be necessary to implement anyway to filter out leading edge spikes on the primary current signal. What are the specs of your converter?

[Alex-lab]

The first thing that comes to mind is that your blanking is implemented such that transitions in the current comparator are ignored during the blanking window. This is as opposed to the transitions being delayed until the end of the blanking window.

Yes, I know about these modes, and it should be correct, otherwise this false-triggering would happen for any DAC setpoint and the system would be unable to regulate.

I would also add a second current comparator whose threshold is always higher (maybe at the maximum peak current spec) than the first comparator, in order to limit peak current to a sane value in case the first comparator is missed.

Hm, quite interesting approach, I will try to work around using it.

instead of the duty cycle you base this on when the peak current set point gets below a certain threshold and start skipping pulses then?

When I limit pulse width, I limit the output voltage. When I limit DAC setpoint, I limit the current.
I am attempting to properly manage low impedance load conditions (close to short circuit). In other words, to reduce voltage if the load is of low impedance, this what is happening under voltage control. However, if the current is limited then period skipping occurs on high-Z loads with little current, which is not really practical.

What I am thinking is to estimate the load impedance from voltage/current ratio, and manage this situation in software.
I also heard that current mode, can be turned into voltage mode if the slope compensation is too high. Thus another option may be to stop reducing DAC below certain min limit, and than reduce the slope only, which max value shut down converter in period skipping mode. There should not be any problem to implement as both DAC and Slope are available from the same register.

[Sniper1]

The first thing that comes to mind is that your blanking is implemented such that transitions in the current comparator are ignored during the blanking window. This is as opposed to the transitions being delayed until the end of the blanking window.

Yes, I know about these modes, and it should be correct, otherwise this false-triggering would happen for any DAC setpoint and the system would be unable to regulate.

I would also add a second current comparator whose threshold is always higher (maybe at the maximum peak current spec) than the first comparator, in order to limit peak current to a sane value in case the first comparator is missed.

Hm, quite interesting approach, I will try to work around using it.

instead of the duty cycle you base this on when the peak current set point gets below a certain threshold and start skipping pulses then?

When I limit pulse width, I limit the output voltage. When I limit DAC setpoint, I limit the current.
I am attempting to properly manage low impedance load conditions (close to short circuit). In other words, to reduce voltage if the load is of low impedance, this what is happening under voltage control. However, if the current is limited then period skipping occurs on high-Z loads with little current, which is not really practical.

What I am thinking is to estimate the load impedance from voltage/current ratio, and manage this situation in software.
I also heard that current mode, can be turned into voltage mode if the slope compensation is too high. Thus another option may be to stop reducing DAC below certain min limit, and than reduce the slope only, which max value shut down converter in period skipping mode. There should not be any problem to implement as both DAC and Slope are available from the same register.

How is it going? did you figure it out?

[multipla]

When I limit pulse width, I limit the output voltage. When I limit DAC setpoint, I limit the current.
I am attempting to properly manage low impedance load conditions (close to short circuit). In other words, to reduce voltage if the load is of low impedance, this what is happening under voltage control. However, if the current is limited then period skipping occurs on high-Z loads with little current, which is not really practical.

What I am thinking is to estimate the load impedance from voltage/current ratio, and manage this situation in software.
I also heard that current mode, can be turned into voltage mode if the slope compensation is too high. Thus another option may be to stop reducing DAC below certain min limit, and than reduce the slope only, which max value shut down converter in period skipping mode. There should not be any problem to implement as both DAC and Slope are available from the same register.

Do you have a normal rectifier on the secondary or a synchronous one? That affects the waveforms and behaviour quite a lot, especially in low load conditions.
In dead short circuit situations it's easier to measure and control the current instead, if you can do this somehow...

[euthon]

Hi Alex!

Would you mind sharing some details on how you configure the HRTIM peripheral for phase shifting? Right now I’m trying to build a voltage mode phase shifted full bridge.

Here is the HRTIM configuration I came up with so far. The timer A drives the non-modulated bridge leg. The timer B drives the modulated (leading) leg. The Master timer is used for synchronization. All three timers are set to the same period. The timer A is configured in half mode and is reset on master’s period. The timer B is also set to half mode and is reset on one of the master’s compare registers. Thus, the value in that master compare register determines the phase shift between the timers A and B.

This config seems to work, but I’m wondering if it can be done more efficiently, reliably, etc.