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| PCMC+PSFB on STM32 is it possible? |
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| Alex-lab:
--- Quote from: mtwieg on September 22, 2024, 04:35:15 pm --- why you'd need to differentiate the edges of the pulse in such a way. --- End quote --- I suppose, it is because on the over current event we need to toggle the output states, but on the normal ending (if no comp event) we should switch outputs to specific levels. All other things like blanking and slope compensation using DAC are simple in implementation. My question was about a particular table from the manual, but it seems work fine. --- Quote ---Agreed, that is strange. I wonder how the magnetizing flux is reset properly... --- End quote --- In my future design I am planning to use unipolar circuit as in the datasheet for UCC28950. |
| Alex-lab:
I am wondering if I need to change the slope magnitude for low duty cycle? I know that the DAC value controls the peak current, but what is about the slope at low duty cycle? Some appnotes (SLUA837) states that it is a good thing to have slope compensation even at low duty cycles. Despite it is mainly designed for 50% and over. Just for more predictable behaviour in noisy environment etc. May it be practical to reduce the slope at low duty cycles? |
| mtwieg:
--- Quote from: Alex-lab on September 24, 2024, 12:27:10 pm ---I am wondering if I need to change the slope magnitude for low duty cycle? I know that the DAC value controls the peak current, but what is about the slope at low duty cycle? Some appnotes (SLUA837) states that it is a good thing to have slope compensation even at low duty cycles. Despite it is mainly designed for 50% and over. Just for more predictable behaviour in noisy environment etc. May it be practical to reduce the slope at low duty cycles? --- End quote --- It's been a while since I looked closely at the math of slope compensation/subharmonic oscillation. Yes, having some slope compensation can be beneficial even when D<50%. The D>=50% threshold is based on the assumption that there are no delays in the system. For example if your controller has a delay equivalent to 5% of a PWM period, then you should have slope compensation at D>=45%. Having a bit of slope compensation might be justifiable, but I would rely on thorough empirical testing. Changing the slope dynamically will act as a perturbation to the system, so I would not take that approach unless you've modeled everything correctly and can show a clear benefit. |
| Alex-lab:
Thanks. For now I just keep it constant and it works as expected. Really impressive set point step response! But I have one more question. Previously, working in voltage mode, when controller reduced the duty cycle below a certain minimum level (<3%), the PWM signal was shut down to zero and overall converter was turned into a "period skipping" mode. Using PCM control I have no direct access to the current duty cycle value, thus cannot implement the same period skipping approach. As a result, when pulses are getting shorter than some critical value, the phase of variable leg jumps by ~180 deg., which cause almost 100% power. It looks like comparator is triggered twice. Of course, this behaviour is unwanted as can easily damage the device. What can be used as a parameter to prevent this situation? I tried to use DAC value, to skip period if it goes below some small value (<5%), it skips periods, but the phase is still inverted... May extended Blanking of current transformer signal help in this case? Is there any special name for this situation? Thank you. |
| mtwieg:
--- Quote from: Alex-lab on October 27, 2024, 01:55:30 pm ---But I have one more question. Previously, working in voltage mode, when controller reduced the duty cycle below a certain minimum level (<3%), the PWM signal was shut down to zero and overall converter was turned into a "period skipping" mode. Using PCM control I have no direct access to the current duty cycle value, thus cannot implement the same period skipping approach. As a result, when pulses are getting shorter than some critical value, the phase of variable leg jumps by ~180 deg., which cause almost 100% power. It looks like comparator is triggered twice. Of course, this behaviour is unwanted as can easily damage the device. What can be used as a parameter to prevent this situation? I tried to use DAC value, to skip period if it goes below some small value (<5%), it skips periods, but the phase is still inverted... May extended Blanking of current transformer signal help in this case? Is there any special name for this situation? Thank you. --- End quote --- Hmm could you show an example waveform of what you're seeing? The first thing that comes to mind is that your blanking is implemented such that transitions in the current comparator are ignored during the blanking window. This is as opposed to the transitions being delayed until the end of the blanking window. The former case can lead to issues like what you describe (but it's probably not the only way). If possible I would also add a second current comparator whose threshold is always higher (maybe at the maximum peak current spec) than the first comparator, in order to limit peak current to a sane value in case the first comparator is missed. At least as a hack until a better solution is found. If this is your problem, and there's no way to make the blanking delay the comparator trip, then another workaround may be to implement a minimum |
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