Phantom power reduction in AC/DC power converters [Which IC?]

[rbe]

I am looking at acquiring an IC that could disconnect 3 ADC lines from high voltage points during no load operation for AC/DC power converter.
I found Champion CM03 https://www.alldatasheet.com/datasheet-pdf/pdf/1222811/CHAMP/CM03X.html part that does exactly what I need, however it is a Taiwanese manufacturer and I believe it is not available on usual distributors like DigiKey, Mouser, etc.
Can anyone recommend me a similar IC? I have looked for alternative solutions out there but no success so far.
In addition, I have already used discrete NMOS devices to achieve this, but due to size constraint I am leaning more towards a single IC solution.
The schematic and symbol are attached below for reference.

Thanks a lot  in advance!

[f4eru]

Hello,

I would recommend against having 300V between SOIC pins (small distance)
-> use 3x BSS127, that is similarily small

[mtwieg]

It's unclear what you're trying to acheive... did you mean "DC lines" or "AC lines" instead of "ADC lines"? Do you have a reference schematic showing how a chip like this would be connected?

[rbe]

Both high voltage AC and DC lines are disconnected after the voltage divider, thus the highest voltage present at those pins will be up to 200V.
Yes BSS127H6327XTSA2 is exactly what I use already in this design.

[rbe]

However, 200V is still too large for 1.27 mm pitch SOIC-8 package. I might just stick with discrete NMOS solution instead. Thanks for your help everyone.
I could redesign voltage divider to allow for even smaller voltage to appear between those pins, but that is not the solution I want/need.

[mtwieg]

Both high voltage AC and DC lines are disconnected after the voltage divider, thus the highest voltage present at those pins will be up to 200V.
Yes BSS127H6327XTSA2 is exactly what I use already in this design.

Ok so the op amp circuit is for measuring the high voltage input (VACL to VACN), and you'd like to be able to disconnect this circuit from the high voltage to reduce loading.

You also mention a voltage divider, but I don't think that's shown on the schematic. A voltage divider on the high voltage would also draw phantom power, right?

Also your schematic wouldn't be effective if the input is AC (or, more generally, if either VACN or VACL go negative with respect to your circuit GND), as Q11 and Q14 will only block current in one direction. To work with AC you'd need to replace each with an antiseries pair of FETs (like in a SSR).

Aside from that, yes I agree that 200V between pins of a SOIC is not a good idea (IPC 2221B recommends at least 50mil clearance for 200V).

[NiHaoMike]

I wonder how long it would take for the minuscule amount of power saved by disconnecting sense resistors to offset the energy used to manufacture the parts used to implement that disconnect. A 3.3M sense resistance connected to 240V would dissipate 17.5mW, at that rate it would use 0.153kWh in a year. Never mind the additional failure points of the added complexity, which would only take a tiny additional failure rate for the resources used to repair/replace the devices to erase such a small savings.

[rbe]

There are more HV lines that these 3M3 resistors are connected to and thus the power consumption would be higher than what you indicated, but I agree with you, the savings are arguable even in the long run. However, this is imposed by standards/customers and must be implemented regardless of what I think about it 

[mtwieg]

I've seen similar tricks used in medical devices. Power consumption isn't the issue, but rather current leaking from AC mains to the secondary side which might find its way to a patient/operator.